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1. 发明授权

US5564117A Computer system including a page printer controller including a single chip supercalar microprocessor with graphical functional units 失效
标题翻译：计算机系统包括页面打印机控制器，其包括具有图形功能单元的单芯片超标准微处理器
公开(公告)号：US5564117A
公开(公告)日：1996-10-08
申请号：US468083
申请日：1995-06-06
申请人： Derek J. Lentz , Johannes Wang , Trevor Deosaran , Linley M. Young , Kian-Chin Yap , Le T. Nguyen , Makoto Matsubayashi , Te-Li Lau
发明人： Derek J. Lentz , Johannes Wang , Trevor Deosaran , Linley M. Young , Kian-Chin Yap , Le T. Nguyen , Makoto Matsubayashi , Te-Li Lau
IPC分类号： B41J5/30 , B41J29/38 , G06F3/12 , G06F9/308 , G06F15/78 , G06K15/00 , G06K15/02 , G06T1/20 , G06F15/16
CPC分类号： G06F9/30018 , G06K15/00 , G06K15/02 , G06K2215/0002 , G06K2215/0005 , G06K2215/004 , G06K2215/0054 , G06K2215/0062 , G06K2215/0071 , G06K2215/0082
摘要： A VLSIC page printer controller includes an instruction processor which responds to a host computer and a printer video processor for accessing data from memory under the control of the instruction processor and serializing data for transfer to a printer through a video port. An I/O interface interconnects the printer controller with an I/O bus to which is connected a host computer, memory devices, and other peripheral devices. An internal memory interface connects the printer controller to memory, and the printer video processor is provided with direct memory access (DMA). Data and instruction caches and an instruction ROM are provided on-chip. A RISC instruction processing unit includes as an integral part thereof the special function, circuits of orthogonal rotator, bit/byte mirror, and pixel modification.
摘要翻译： VLSIC页面打印机控制器包括指令处理器，其响应于主计算机和打印机视频处理器，用于在指令处理器的控制下从存储器访问数据，并串行化数据以通过视频端口传送到打印机。 I / O接口将打印机控制器与连接到主机，存储设备和其他外围设备的I / O总线互连。内部存储器接口将打印机控制器连接到存储器，并且打印机视频处理器具有直接存储器访问（DMA）。数据和指令高速缓存以及指令ROM片上提供。 RISC指令处理单元作为其整体部分包括特殊功能，正交旋转器的电路，位/字节镜和像素修改。

2. 发明授权

US5559951A Page printer controller including a single chip superscalar microprocessor with graphics functional units 失效
标题翻译：页面打印机控制器，包括具有图形功能单元的单芯片超标量微处理器
公开(公告)号：US5559951A
公开(公告)日：1996-09-24
申请号：US383015
申请日：1995-02-03
申请人： Derek J. Lentz , Johannes Wang , Trevor Deosaran , Linley M. Young , Kian-Chin Yap , Le Trong Nguyen , Makoto Matsubayashi , Te-Li Lau
发明人： Derek J. Lentz , Johannes Wang , Trevor Deosaran , Linley M. Young , Kian-Chin Yap , Le Trong Nguyen , Makoto Matsubayashi , Te-Li Lau
IPC分类号： B41J5/30 , B41J29/38 , G06F3/12 , G06F9/308 , G06F15/78 , G06K15/00 , G06K15/02 , G06T1/20 , G06F15/16
CPC分类号： G06F9/30018 , G06K15/00 , G06K15/02 , G06K2215/0002 , G06K2215/0005 , G06K2215/004 , G06K2215/0054 , G06K2215/0062 , G06K2215/0071 , G06K2215/0082
摘要： A VLSIC page printer controller includes an instruction processor which responds to a host computer and a printer video processor for accessing data from memory under the control of the instruction processor and serializing data for transfer to a printer through a video port. An I/0 interface interconnects the printer controller with an I/O bus to which is connected a host computer, memory devices, and other peripheral devices. An internal memory interface connects the printer controller to memory, and the printer video processor is provided with direct memory access (DMA). Data and instruction caches and an instruction ROM are provided on-chip. A RISC instruction processing unit includes as an integral part thereof the special function circuits of orthogonal rotator, bit/byte mirror, and pixel modification.
摘要翻译： VLSIC页面打印机控制器包括指令处理器，其响应于主计算机和打印机视频处理器，用于在指令处理器的控制下从存储器访问数据，并串行化数据以通过视频端口传送到打印机。 I / O接口将打印机控制器与连接到主机，存储设备和其他外围设备的I / O总线互连。内部存储器接口将打印机控制器连接到存储器，并且打印机视频处理器具有直接存储器访问（DMA）。数据和指令高速缓存以及指令ROM片上提供。 RISC指令处理单元作为其整体部分包括正交旋转器的特殊功能电路，位/字节镜和像素修改。

3. 发明授权

US5394515A Page printer controller including a single chip superscalar microprocessor with graphics functional units 失效
标题翻译：页面打印机控制器，包括具有图形功能单元的单芯片超标量微处理器
公开(公告)号：US5394515A
公开(公告)日：1995-02-28
申请号：US267646
申请日：1994-06-28
申请人： Derek J. Lentz , Johannes Wang , Trevor Deosaran , Linley M. Young , Kian-Chin Yap , Le Trong Nguyen , Makoto Matsubayashi , Te-Li Lau
发明人： Derek J. Lentz , Johannes Wang , Trevor Deosaran , Linley M. Young , Kian-Chin Yap , Le Trong Nguyen , Makoto Matsubayashi , Te-Li Lau
IPC分类号： B41J5/30 , B41J29/38 , G06F3/12 , G06F9/308 , G06F15/78 , G06K15/00 , G06K15/02 , G06T1/20 , G06F15/00
CPC分类号： G06F9/30018 , G06K15/00 , G06K15/02 , G06K2215/0002 , G06K2215/0005 , G06K2215/004 , G06K2215/0054 , G06K2215/0062 , G06K2215/0071 , G06K2215/0082
摘要： A VLSIC page printer controller includes an instruction processor which responds to a host computer and a printer video processor for accessing data from memory under the control of the instruction processor and serializing data for transfer to a printer through a video port. An I/O interface interconnects the printer controller with an I/O bus to which is connected a host computer, memory devices, and other peripheral devices. An internal memory interface connects the printer controller to memory, and the printer video processor is provided with direct memory access (DMA). Data and instruction caches and an instruction ROM are provided on-chip. A RISC instruction processing unit includes as an integral part thereof the special function circuits of orthogonal rotator, bit/byte mirror, and pixel modification.
摘要翻译： VLSIC页面打印机控制器包括指令处理器，其响应于主计算机和打印机视频处理器，用于在指令处理器的控制下从存储器访问数据，并串行化数据以通过视频端口传送到打印机。 I / O接口将打印机控制器与连接到主机，存储设备和其他外围设备的I / O总线互连。内部存储器接口将打印机控制器连接到存储器，并且打印机视频处理器具有直接存储器访问（DMA）。数据和指令高速缓存以及指令ROM片上提供。 RISC指令处理单元作为其整体部分包括正交旋转器的特殊功能电路，位/字节镜和像素修改。

4. 发明授权

US07958337B2 System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor 失效
标题翻译：大量同时退出超标量微处理器中的一组指令的系统和方法
公开(公告)号：US07958337B2
公开(公告)日：2011-06-07
申请号：US12393257
申请日：2009-02-26
申请人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
发明人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： An apparatus and method for executing instructions having a program order. The apparatus comprising a temporary buffer, tag assignment logic, a plurality of functional units, a plurality of data paths, a register array, a retirement control block, and a superscalar instruction retirement unit. The temporary buffer includes a plurality of temporary buffer locations to store result data for executed instructions, wherein the temporary buffer locations are arranged in a plurality of groups of temporary buffer locations. The tag assignment logic is configured to concurrently assign a tag to each instruction in a first set of instructions, wherein the tags are assigned such that the respective tag assigned to each of the instructions in the first set of instructions identifies a different one of the temporary buffer locations in a first one of the groups of temporary buffer locations.
摘要翻译：一种用于执行具有程序顺序的指令的装置和方法。该装置包括临时缓冲器，标签分配逻辑，多个功能单元，多个数据路径，寄存器阵列，退休控制块和超标量指令退出单元。临时缓冲器包括多个临时缓冲器位置，用于存储执行指令的结果数据，其中临时缓冲器位置被布置在多组临时缓冲器位置中。标签分配逻辑被配置为在第一组指令中同时向每个指令分配标签，其中分配标签使得分配给第一组指令中的每个指令的相应标签识别临时的缓冲区位于第一组临时缓冲区中。

5. 发明申请

US20090158014A1 System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor 失效
标题翻译：用于在超标量微处理器中同时退出一组指令的系统和方法
公开(公告)号：US20090158014A1
公开(公告)日：2009-06-18
申请号：US12393257
申请日：2009-02-26
申请人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
发明人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
IPC分类号： G06F9/312
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： An apparatus and method for executing instructions having a program order. The apparatus comprising a temporary buffer, tag assignment logic, a plurality of functional units, a plurality of data paths, a register array, a retirement control block, and a superscalar instruction retirement unit. The temporary buffer includes a plurality of temporary buffer locations to store result data for executed instructions, wherein the temporary buffer locations are arranged in a plurality of groups of temporary buffer locations. The tag assignment logic is configured to concurrently assign a tag to each instruction in a first set of instructions, wherein the tags are assigned such that the respective tag assigned to each of the instructions in the first set of instructions identifies a different one of the temporary buffer locations in a first one of the groups of temporary buffer locations.
摘要翻译：一种用于执行具有程序顺序的指令的装置和方法。该装置包括临时缓冲器，标签分配逻辑，多个功能单元，多个数据路径，寄存器阵列，退休控制块和超标量指令退出单元。临时缓冲器包括多个临时缓冲器位置，用于存储执行指令的结果数据，其中临时缓冲器位置被布置在多组临时缓冲器位置中。标签分配逻辑被配置为在第一组指令中同时向每个指令分配标签，其中分配标签使得分配给第一组指令中的每个指令的相应标签识别临时的缓冲区位于第一组临时缓冲区中。

6. 发明授权

US06920548B2 System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor 失效
公开(公告)号：US06920548B2
公开(公告)日：2005-07-19
申请号：US10815742
申请日：2004-04-02
申请人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
发明人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.

7. 发明授权

US07934078B2 System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor 失效
标题翻译：大量同时退出超标量微处理器中的一组指令的系统和方法
公开(公告)号：US07934078B2
公开(公告)日：2011-04-26
申请号：US12212361
申请日：2008-09-17
申请人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
发明人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.
摘要翻译：一种用于在超标量微处理器中停止指令的系统和方法，该系统和方法执行包括具有预定程序顺序的一组指令的程序，所述退出系统用于同时停止由微处理器执行或不按顺序执行的指令组。退休系统包括：完成块，用于监视指令的状态以确定已经执行了哪个指令或指令组，用于确定每个执行的指令是否可取回的退出控制块;用于存储执行的指令结果的临时缓冲器程序顺序和用于存储可取样指令结果的寄存器阵列。此外，退休控制块还通过将其结果从临时缓冲器同时传送到寄存器阵列来进一步控制被确定为可延展的一组指令的退出，并且通过将它们的结果直接存储在寄存器阵列中来依次执行的指令。该方法包括以下步骤：监视指令的状态以确定已经执行了哪组指令，确定每个被执行的指令是否可以被取消，将在程序顺序中执行的指令的结果存储在临时缓冲器中，存储可检索指令结果一个寄存器阵列，并通过将它们的结果从临时缓冲器同时传送到寄存器阵列，并且将其结果直接存储在寄存器阵列中，按顺序执行退出指令，并退出一组可重试指令。

8. 发明授权

US07516305B2 System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor 失效
公开(公告)号：US07516305B2
公开(公告)日：2009-04-07
申请号：US11642625
申请日：2006-12-21
申请人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
发明人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.

9. 发明申请

US20090013155A1 System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor 失效
标题翻译：用于在超标量微处理器中同时退出一组指令的系统和方法
公开(公告)号：US20090013155A1
公开(公告)日：2009-01-08
申请号：US12212361
申请日：2008-09-17
申请人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
发明人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
IPC分类号： G06F9/30
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.
摘要翻译：一种用于在超标量微处理器中停止指令的系统和方法，该系统和方法执行包括具有预定程序顺序的一组指令的程序，所述退出系统用于同时停止由微处理器执行或不按顺序执行的指令组。退休系统包括：完成块，用于监视指令的状态以确定已经执行了哪个指令或指令组，用于确定每个执行的指令是否可取回的退出控制块;用于存储执行的指令结果的临时缓冲器程序顺序和用于存储可取样指令结果的寄存器阵列。此外，退休控制块还通过将其结果从临时缓冲器同时传送到寄存器阵列来进一步控制确定为可延展的一组指令的退役，并且通过将其结果直接存储在寄存器阵列中来依次执行的指令。该方法包括以下步骤：监视指令的状态以确定已经执行了哪组指令，确定每个被执行的指令是否可以被取消，将在程序顺序中执行的指令的结果存储在临时缓冲器中，存储可检索指令结果一个寄存器阵列，并通过将它们的结果从临时缓冲器同时传送到寄存器阵列，并且将其结果直接存储在寄存器阵列中，按顺序执行退出指令，并退出一组可重试指令。

10. 发明申请

US20050228973A1 System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor 失效
标题翻译：大量同时退出超标量微处理器中的一组指令的系统和方法
公开(公告)号：US20050228973A1
公开(公告)日：2005-10-13
申请号：US11149227
申请日：2005-06-10
申请人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
发明人： Johannes Wang , Sanjiv Garg , Trevor Deosaran
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3012 , G06F9/3013 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3857 , G06F9/3863 , G06F9/3885
摘要： An system and method for retiring instructions in a superscalar microprocessor which executes a program comprising a set of instructions having a predetermined program order, the retirement system for simultaneously retiring groups of instructions executed in or out of order by the microprocessor. The retirement system comprises a done block for monitoring the status of the instructions to determine which instruction or group of instructions have been executed, a retirement control block for determining whether each executed instruction is retirable, a temporary buffer for storing results of instructions executed out of program order, and a register array for storing retirable-instruction results. In addition, the retirement control block further controls the retiring of a group of instructions determined to be retirable, by simultaneously transferring their results from the temporary buffer to the register array, and retires instructions executed in order by storing their results directly in the register array. The method comprises the steps of monitoring the status of the instructions to determine which group of instructions have been executed, determining whether each executed instruction is retirable, storing results of instructions executed out of program order in a temporary buffer, storing retirable-instruction results in a register array and retiring a group of retirable instructions by simultaneously transferring their results from the temporary buffer to the register array, and retiring instructions executed in order by storing their results directly in the register array.
摘要翻译：一种用于在超标量微处理器中停止指令的系统和方法，该系统和方法执行包括具有预定程序顺序的一组指令的程序，所述退出系统用于同时停止由微处理器执行或不按顺序执行的指令组。退休系统包括：完成块，用于监视指令的状态以确定已经执行了哪个指令或指令组，用于确定每个执行的指令是否可取回的退出控制块;用于存储执行的指令结果的临时缓冲器程序顺序和用于存储可取样指令结果的寄存器阵列。此外，退休控制块还通过将其结果从临时缓冲器同时传送到寄存器阵列来进一步控制确定为可延展的一组指令的退役，并且通过将其结果直接存储在寄存器阵列中来依次执行的指令。该方法包括以下步骤：监视指令的状态以确定已经执行了哪组指令，确定每个被执行的指令是否可以被取消，将在程序顺序中执行的指令的结果存储在临时缓冲器中，存储可检索指令结果一个寄存器阵列，并通过将它们的结果从临时缓冲器同时传送到寄存器阵列，并且将其结果直接存储在寄存器阵列中，按顺序执行退出指令，并退出一组可重试指令。

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