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1. 发明申请

US20070152295A1 Metal-insulator-metal capacitor structure having low voltage dependence 失效
标题翻译：具有低电压依赖性的金属 - 绝缘体 - 金属电容器结构
公开(公告)号：US20070152295A1
公开(公告)日：2007-07-05
申请号：US11322209
申请日：2005-12-29
申请人： Der-Chyang Yeh , Chie-Iuan Lin , Chuan-Ying Lee , Y. Chao , Ming-Hsien Chen
发明人： Der-Chyang Yeh , Chie-Iuan Lin , Chuan-Ying Lee , Y. Chao , Ming-Hsien Chen
IPC分类号： H01L29/00
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor capacitor device. A dielectric layer is on a substrate. A stack capacitor structure is disposed in the dielectric layer and comprises first and overlying second MIM capacitors electrically connected in parallel. The first and second MIM capacitors have individual upper and lower electrode plates and different compositions of capacitor dielectric layers.
摘要翻译：一种半导体电容器件。电介质层在衬底上。堆叠电容器结构设置在电介质层中，并且包括并联电连接的第一和第二MIM电容器。第一和第二MIM电容器具有单独的上电极板和下电极板以及电容器介电层的不同组成。

2. 发明授权

US07763923B2 Metal-insulator-metal capacitor structure having low voltage dependence 失效
标题翻译：具有低电压依赖性的金属 - 绝缘体 - 金属电容器结构
公开(公告)号：US07763923B2
公开(公告)日：2010-07-27
申请号：US11322209
申请日：2005-12-29
申请人： Der-Chyang Yeh , Chie-Iuan Lin , Chuan-Ying Lee , Yi-Ting Chao , Ming-Hsien Chen
发明人： Der-Chyang Yeh , Chie-Iuan Lin , Chuan-Ying Lee , Yi-Ting Chao , Ming-Hsien Chen
IPC分类号： H01L27/108
CPC分类号： H01L23/5223 , H01L28/60 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor capacitor device. A dielectric layer is on a substrate. A stack capacitor structure is disposed in the dielectric layer and comprises first and overlying second MIM capacitors electrically connected in parallel. The first and second MIM capacitors have individual upper and lower electrode plates and different compositions of capacitor dielectric layers.
摘要翻译：一种半导体电容器件。电介质层在衬底上。堆叠电容器结构设置在电介质层中，并且包括并联电连接的第一和第二MIM电容器。第一和第二MIM电容器具有单独的上电极板和下电极板以及电容器介电层的不同组成。

3. 发明授权

US07511346B2 Design of high-frequency substrate noise isolation in BiCMOS technology 有权
标题翻译： BiCMOS技术中高频衬底噪声隔离设计
公开(公告)号：US07511346B2
公开(公告)日：2009-03-31
申请号：US11320255
申请日：2005-12-27
申请人： Der-Chyang Yeh , Chuan-Ying Lee , Victor P. C. Yeh
发明人： Der-Chyang Yeh , Chuan-Ying Lee , Victor P. C. Yeh
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/761 , H01L21/823878
摘要： A high-frequency noise isolation structure and a method for forming the same are provided. The noise isolation structure isolates a first device region and a second device region over a semiconductor substrate. The noise isolation structure preferably includes a sinker region substantially encircling a first device region, a buried layer underlying the first device region and joining the sinker region, a deep guard ring substantially encircling the sinker region, and a deep trench oxide region substantially encircling the sinker region. The isolation structure further includes a wide guard ring between the first and the second device regions. The sinker region and the buried region preferably have a high impurity concentration. Integrated circuits to be noise decoupled are preferably formed in the respective first and second device regions.
摘要翻译：提供高频噪声隔离结构及其形成方法。噪声隔离结构隔离半导体衬底上的第一器件区域和第二器件区域。噪声隔离结构优选地包括基本上环绕第一器件区域的沉降片区域，位于第一器件区域下方的接合沉积片区域，基本上环绕沉降片区域的深保护环，以及基本上环绕沉降片的深沟槽氧化物区域地区。隔离结构还包括在第一和第二器件区之间的宽保护环。沉降片区域和掩埋区域优选具有高杂质浓度。优选地，在相应的第一和第二设备区域中形成要进行噪声去耦的集成电路。

4. 发明申请

US20070145489A1 Design of high-frequency substrate noise isolation in BiCMOS technology 有权
标题翻译： BiCMOS技术中高频衬底噪声隔离设计
公开(公告)号：US20070145489A1
公开(公告)日：2007-06-28
申请号：US11320255
申请日：2005-12-27
申请人： Der-Chyang Yeh , Chuan-Ying Lee , Victor Yeh
发明人： Der-Chyang Yeh , Chuan-Ying Lee , Victor Yeh
IPC分类号： H01L29/76
CPC分类号： H01L21/761 , H01L21/823878
摘要： A high-frequency noise isolation structure and a method for forming the same are provided. The noise isolation structure isolates a first device region and a second device region over a semiconductor substrate. The noise isolation structure preferably includes a sinker region substantially encircling a first device region, a buried layer underlying the first device region and joining the sinker region, a deep guard ring substantially encircling the sinker region, and a deep trench oxide region substantially encircling the sinker region. The isolation structure further includes a wide guard ring between the first and the second device regions. The sinker region and the buried region preferably have a high impurity concentration. Integrated circuits to be noise decoupled are preferably formed in the respective first and second device regions.
摘要翻译：提供高频噪声隔离结构及其形成方法。噪声隔离结构隔离半导体衬底上的第一器件区域和第二器件区域。噪声隔离结构优选地包括基本上环绕第一器件区域的沉降片区域，位于第一器件区域下方的接合沉积片区域的基底层，基本上环绕沉降片区域的深保护环，以及基本上环绕沉降片的深沟槽氧化物区域地区。隔离结构还包括在第一和第二器件区之间的宽保护环。沉降片区域和掩埋区域优选具有高杂质浓度。优选地，在相应的第一和第二设备区域中形成要进行噪声去耦的集成电路。

5. 发明授权

US07759764B2 Elevated bipolar transistor structure 失效
标题翻译：高双极晶体管结构
公开(公告)号：US07759764B2
公开(公告)日：2010-07-20
申请号：US11698346
申请日：2007-01-26
申请人： Chuan-Ying Lee , Denny Duan-lee Tang
发明人： Chuan-Ying Lee , Denny Duan-lee Tang
IPC分类号： H01L29/00 , H01L29/70
CPC分类号： H01L29/73 , H01L27/2445 , H01L29/0804 , H01L29/1004 , H01L29/66242 , H01L29/66272 , H01L29/66318 , H01L29/732 , H01L29/7371 , H01L29/7378 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A semiconductor structure includes a substrate; an isolation structure in the substrate, wherein the isolation structure defines a region therein; a first semiconductor region having at least a portion in the region defined by the isolation structure, wherein the first semiconductor region is of a first conductivity type; a second semiconductor region on the first semiconductor region, wherein the second semiconductor region is of a second conductivity type opposite the first conductivity type; and a third semiconductor region of the first conductivity type on the second semiconductor region, wherein the third semiconductor region has at least a portion higher than a top surface of the isolation structure.
摘要翻译：半导体结构包括基板; 衬底中的隔离结构，其中所述隔离结构在其中限定区域; 第一半导体区域，其具有由所述隔离结构限定的区域中的至少一部分，其中所述第一半导体区域是第一导电类型; 在所述第一半导体区域上的第二半导体区域，其中所述第二半导体区域是与所述第一导电类型相反的第二导电类型; 以及在第二半导体区域上具有第一导电类型的第三半导体区域，其中第三半导体区域具有比隔离结构的顶表面高至少一部分。

6. 发明申请

US20060278928A1 Semiconductor layout structure for ESD protection circuits 有权
标题翻译： ESD保护电路的半导体布局结构
公开(公告)号：US20060278928A1
公开(公告)日：2006-12-14
申请号：US11152440
申请日：2005-06-14
申请人： Yi-Hsun Wu , Kuan-Lun Chang , Chuan-Ying Lee , Jian-Hsing Lee
发明人： Yi-Hsun Wu , Kuan-Lun Chang , Chuan-Ying Lee , Jian-Hsing Lee
IPC分类号： H01L23/62
CPC分类号： H01L27/0262
摘要： A semiconductor layout structure for an electrostatic discharge (ESD) protection circuit is disclosed. The semiconductor layout structure includes a first area, in which one or more devices are constructed for functioning as a silicon controlled rectifier, and a second area, in which at least one device is constructed for functioning as a trigger source that provides a triggering current to trigger the silicon controlled rectifier for dissipating ESD charges during an ESD event. The first area and the second area are placed adjacent to one another without having a resistance area physically interposed or electrically connected therebetween, such that the triggering current received by the silicon controlled rectifier is increased during the ESD event.
摘要翻译：公开了一种用于静电放电（ESD）保护电路的半导体布局结构。半导体布局结构包括第一区域，其中构造一个或多个器件用作可控硅整流器，以及第二区域，其中构造至少一个器件用作触发源，该触发源提供触发电流触发可控硅整流器，以在ESD事件期间耗散ESD电荷。第一区域和第二区域彼此相邻放置，而不会在其间物理地插入或电连接电阻区域，使得在ESD事件期间由可控硅整流器接收的触发电流增加。

7. 发明申请

US20100013020A1 Semiconductor device with semi-insulating substrate portions 有权
标题翻译：具有半绝缘衬底部分的半导体器件
公开(公告)号：US20100013020A1
公开(公告)日：2010-01-21
申请号：US12586688
申请日：2009-09-24
申请人： Wen-Chin Lin , Denny Tang , Chuan-Ying Lee , H. C. Cheng
发明人： Wen-Chin Lin , Denny Tang , Chuan-Ying Lee , H. C. Cheng
IPC分类号： H01L27/06 , H01L29/06
CPC分类号： H01L21/76 , H01L21/263 , H01L21/26506 , H01L21/266 , H01L21/823481 , H01L21/823878 , H01L27/08
摘要： A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.
摘要翻译：半导体衬底包括在半导体子结构上形成的图案化硬掩模膜的开口下方的半绝缘部分，其厚度足以防止带电粒子通过硬掩模。半绝缘部分包括带电粒子并且可以深深地延伸到半导体衬底中并且电绝缘形成在半绝缘部分的相对侧上的器件。带电粒子可以有利地是质子，并且由图案化的硬掩模膜覆盖的另外的基底部分基本上没有带电粒子。

8. 发明申请

US20080099863A1 Elevated bipolar transistor structure 失效
标题翻译：高双极晶体管结构
公开(公告)号：US20080099863A1
公开(公告)日：2008-05-01
申请号：US11698346
申请日：2007-01-26
申请人： Chuan-Ying Lee , Denny Duan-Iee Tang
发明人： Chuan-Ying Lee , Denny Duan-Iee Tang
IPC分类号： H01L29/82
CPC分类号： H01L29/73 , H01L27/2445 , H01L29/0804 , H01L29/1004 , H01L29/66242 , H01L29/66272 , H01L29/66318 , H01L29/732 , H01L29/7371 , H01L29/7378 , H01L45/06 , H01L45/1233 , H01L45/144 , H01L45/1675
摘要： A semiconductor structure includes a substrate; an isolation structure in the substrate, wherein the isolation structure defines a region therein; a first semiconductor region having at least a portion in the region defined by the isolation structure, wherein the first semiconductor region is of a first conductivity type; a second semiconductor region on the first semiconductor region, wherein the second semiconductor region is of a second conductivity type opposite the first conductivity type; and a third semiconductor region of the first conductivity type on the second semiconductor region, wherein the third semiconductor region has at least a portion higher than a top surface of the isolation structure.
摘要翻译：半导体结构包括基板; 衬底中的隔离结构，其中所述隔离结构在其中限定区域; 第一半导体区域，其具有由所述隔离结构限定的区域中的至少一部分，其中所述第一半导体区域是第一导电类型; 在所述第一半导体区域上的第二半导体区域，其中所述第二半导体区域是与所述第一导电类型相反的第二导电类型; 以及在第二半导体区域上具有第一导电类型的第三半导体区域，其中第三半导体区域具有比隔离结构的顶表面高至少一部分。

9. 发明授权

US07964900B2 Semiconductor device with semi-insulating substrate portions 有权
标题翻译：具有半绝缘衬底部分的半导体器件
公开(公告)号：US07964900B2
公开(公告)日：2011-06-21
申请号：US12586688
申请日：2009-09-24
申请人： Wen-Chin Lin , Denny Tang , Chuan-Ying Lee , Hsu Chen Cheng
发明人： Wen-Chin Lin , Denny Tang , Chuan-Ying Lee , Hsu Chen Cheng
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/76 , H01L21/263 , H01L21/26506 , H01L21/266 , H01L21/823481 , H01L21/823878 , H01L27/08
摘要： A semiconductor substrate includes semi-insulating portions beneath openings in a patterned hardmask film formed over a semiconductor substructure to a thickness sufficient to prevent charged particles from passing through the hardmask. The semi-insulating portions include charged particles and may extend deep into the semiconductor substrate and electrically insulate devices formed on opposed sides of the semi-insulating portions. The charged particles may advantageously be protons and further substrate portions covered by the patterned hardmask film are substantially free of the charged particles.
摘要翻译：半导体衬底包括在半导体子结构上形成的图案化硬掩模膜的开口下方的半绝缘部分，其厚度足以防止带电粒子通过硬掩模。半绝缘部分包括带电粒子并且可以深深地延伸到半导体衬底中并且电绝缘形成在半绝缘部分的相对侧上的器件。带电粒子可以有利地是质子，并且由图案化的硬掩模膜覆盖的另外的基底部分基本上没有带电粒子。

10. 发明申请

US20050121744A1 High density MIM capacitor structure and fabrication process 有权
标题翻译：高密度MIM电容器结构及制造工艺
公开(公告)号：US20050121744A1
公开(公告)日：2005-06-09
申请号：US10729034
申请日：2003-12-04
申请人： Kuan-Lun Chang , Chuan-Ying Lee , Chun-Hon Chen
发明人： Kuan-Lun Chang , Chuan-Ying Lee , Chun-Hon Chen
IPC分类号： H01L21/02 , H01L23/522 , H01L27/08 , H01L29/00
CPC分类号： H01L28/40 , H01L23/5223 , H01L27/0805 , H01L2924/0002 , H01L2924/3011 , Y10S438/957 , H01L2924/00
摘要： A stacked integrated circuit (IC) MIM capacitor structure and method for forming the same the MIM capacitor structure including a first MIM capacitor structure formed in a first IMD layer comprising an first upper and first lower electrode portions; at least a second MIM capacitor structure arranged in stacked relationship in an overlying IMD layer comprising a second upper electrode and second lower electrode to form an MIM capacitor stack; wherein, the first lower electrode is arranged in common electrical signal communication comprising metal filled vias with the second upper electrode and the first upper electrode is arranged in common electrical signal communication with the second lower electrode.
摘要翻译：一种用于形成MIM电容器结构的叠层集成电路（IC）MIM电容器结构及方法，包括形成在包括第一上电极部分和第一下电极部分的第一IMD层中的第一MIM电容器结构; 至少第二MIM电容器结构，以层叠的关系布置在包括第二上电极和第二下电极的上覆IMD层中，以形成MIM电容器堆叠; 其中，所述第一下部电极布置成共同的电信号通信，包括金属填充的通孔与所述第二上部电极和所述第一上部电极被布置成与所述第二下部电极共同的电信号通信。

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