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1. 发明授权

US4545036A Sense amplifier with time dependent sensitivity 失效
标题翻译：具有时间灵敏度的感应放大器
公开(公告)号：US4545036A
公开(公告)日：1985-10-01
申请号：US541926
申请日：1983-10-14
申请人： Dennis L. Segers
发明人： Dennis L. Segers
IPC分类号： G11C5/00 , G11C11/4091 , G11C11/40
CPC分类号： G11C11/4091 , G11C5/005
摘要： A dynamic RAM integrated circuit has improved resistance to soft errors caused by alpha particles by changing the trip-point voltage of the sense amplifier from a first value that provides resistance to bit line errors to a second, lower value that provides resistance to cell errors.
摘要翻译：动态RAM集成电路通过将读出放大器的跳变点电压从提供对位线错误的电阻的第一值改变为提供对单元错误的电阻的第二较低值，从而改善了由α粒子引起的对软误差的抵抗力。

2. 发明授权

US4573146A Testing and evaluation of a semiconductor memory containing redundant memory elements 失效
标题翻译：包含冗余存储器元件的半导体存储器的测试和评估
公开(公告)号：US4573146A
公开(公告)日：1986-02-25
申请号：US370171
申请日：1982-04-20
申请人： Andrew C. Graham , Robert J. Proebsting , Dennis L. Segers
发明人： Andrew C. Graham , Robert J. Proebsting , Dennis L. Segers
IPC分类号： G11C29/00 , G11C29/24 , G11C8/00 , G11C11/40
CPC分类号： G11C29/835 , G11C29/24
摘要： A method and apparatus is described for initiating a selected functional mode for a semiconductor memory circuit to determine the implementation of redundant elements in a semiconductor memory. The method for initiating the selected functional mode comprises applying an active state of at least a first of the operational signals to the memory circuit followed by applying an active state of a second of the operational signals to the memory circuit. The timing of the second operational signal relative to the first operational signal is not within the defined specification limits of the first and the second operational signals for conventional data transfer to and from the memory. An example of the selected functional mode is the activation of circuitry (62) which serves to apply a predetermined data state to a redundant column (63) which can be substituted to replace a defective primary column within a memory array. After the memory array has previously received a first data state and the circuit (62) is activated to apply a second data state to the redundant column (63) the memory array is read and each column which produces a second data state is determined to be a redundant column. With knowledge of the column substitution algorithm, it can then be determined which of the redundant columns have been programmed to replace specific original columns. This method can therefore determine the physical configuration of the memory circuit despite the incorporation of redundant elements into the primary memory array.
摘要翻译：描述了用于启动用于半导体存储器电路的选定功能模式以确定半导体存储器中的冗余元件的实现的方法和装置。用于启动所选择的功能模式的方法包括将至少第一操作信号的活动状态施加到存储器电路，然后将第二操作信号的有效状态施加到存储器电路。相对于第一操作信号的第二操作信号的定时不在用于传送到存储器和从存储器的常规数据传输的第一和第二操作信号的规定的限定范围内。所选择的功能模式的示例是激活电路（62），其用于将预定数据状态应用于冗余列（63），冗余列（63）可替代以代替存储器阵列内的有缺陷的主列。在存储器阵列先前已经接收到第一数据状态并且电路（62）被激活以将第二数据状态应用于冗余列（63）之后，存储器阵列被读取，并且产生第二数据状态的每一列被确定为冗余列。利用列替换算法的知识，可以确定哪些冗余列已被编程以替换特定的原始列。因此，尽管将冗余元件并入主存储器阵列中，但是该方法可以确定存储器电路的物理配置。

3. 发明授权

US5249282A Integrated cache memory system with primary and secondary cache memories 失效
标题翻译：具有主缓存和二级缓存的集成缓存系统
公开(公告)号：US5249282A
公开(公告)日：1993-09-28
申请号：US616427
申请日：1990-11-21
申请人： Dennis L. Segers
发明人： Dennis L. Segers
IPC分类号： G06F12/08
CPC分类号： G06F12/0897
摘要： A central processing unit (10) has a cache memory system (24) associated therewith for interfacing with a main memory system (23). The cache memory system (24) includes a primary cache (26) comprised of SRAMS and a secondary cache (28) comprised of DRAM. The primary cache (26) has a faster access than the secondary cache (28). When it is determined that the requested data is stored in the primary cache (26) it is transferred immediately to the central processing unit (10). When it is determined that the data resides only in the secondary cache (28), the data is accessed therefrom and routed to the central processing unit (10) and simultaneously stored in the primary cache (26). If a hit occurs in the primary cache (26), it is accessed and output to a local data bus (32). If only the secondary cache (28) indicates a hit, data is accessed from the appropriate one of the arrays (80)-(86) and transferred through the primary cache ( 26) via transfer circuits (96), (98), (100) and (102) to the data bus (32). Simultaneously therewith, the data is stored in an appropriate one of the arrays (88)-(94). When a hit does not occur in either the secondary cache (28) or the primary cache (26), data is retrieved from the main system memory (23) through a buffer/multiplexer circuit on one side of the secondary cache (28) and passed through both the secondary cache (28) and the primary cache (26) and stored therein in a single operation due to the line for line transfer provided by the transfer circuits (96)-(102).
摘要翻译：中央处理单元（10）具有与其相关联的高速缓冲存储器系统（24），用于与主存储器系统（23）进行接口。高速缓冲存储器系统（24）包括由SRAMS组成的主高速缓存（26）和由DRAM组成的二级高速缓存（28）。主缓存（26）具有比二级高速缓存（28）更快的访问。当确定所请求的数据被存储在主高速缓存（26）中时，它被立即传送到中央处理单元（10）。当确定数据仅驻留在二次高速缓存（28）中时，数据被从其访问并被路由到中央处理单元（10）并且同时存储在主高速缓存（26）中。如果主缓存（26）中发生命中，则它被访问并输出到本地数据总线（32）。如果只有二次高速缓存（28）指示命中，则从阵列（80） - （86）中的适当的一个存取数据，并通过传输电路（96），（98），（ 100）和（102）连接到数据总线（32）。与此同时，数据被存储在阵列（88） - （94）中的适当的一个中。当二级高速缓存（28）或主高速缓存（26）中没有发生命中时，通过二级高速缓存（28）的一侧上的缓冲器/多路复用器电路从主系统存储器（23）检索数据，并且由于传输电路（96） - （102）提供的线路传输线路，通过二级缓存（28）和主高速缓存（26）两者并在其中存储在单个操作中。

4. 发明授权

US5870327A Mixed mode RAM/ROM cell using antifuses 失效
标题翻译：使用反熔丝的混合模式RAM / ROM单元
公开(公告)号：US5870327A
公开(公告)日：1999-02-09
申请号：US963532
申请日：1997-11-03
申请人： Daniel Gitlin , Dennis L. Segers , Michael J. Hart
发明人： Daniel Gitlin , Dennis L. Segers , Michael J. Hart
IPC分类号： G11C7/20 , G11C17/00
CPC分类号： G11C7/20
摘要： A mixed mode RAM/ROM cell includes a volatile memory cell and an antifuse coupled to the cell. In an array of mixed mode memory cells, addressing circuitry is coupled to the volatile memory cells and programming circuitry is coupled to the antifuses. After an antifuse is programmed, the associated memory cell is transformed from a volatile memory to a non-volatile memory. Specifically, during normal operation, a standard supply voltage is provided to all antifuses. Thus, after a power down or power fluctuation, the programmed antifuses ensure subsequent configuration of their respective volatile memory cells.
摘要翻译：混合模式RAM / ROM单元包括易失性存储单元和耦合到单元的反熔丝。在混合模式存储器单元的阵列中，寻址电路耦合到易失性存储器单元，并且编程电路耦合到反熔丝。在反熔丝被编程之后，相关联的存储器单元从易失性存储器转换成非易失性存储器。具体地说，在正常操作期间，向所有反熔丝提供标准电源电压。因此，在断电或功率波动之后，编程的反熔丝确保其各自的易失性存储单元的后续配置。

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