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1. 发明授权

US5942783A Semiconductor device having improved latch-up protection 失效
标题翻译：具有改进的闭锁保护的半导体器件
公开(公告)号：US5942783A
公开(公告)日：1999-08-24
申请号：US594805
申请日：1996-01-31
申请人： Davide Brambilla , Edoardo Botti , Paolo Ferrari
发明人： Davide Brambilla , Edoardo Botti , Paolo Ferrari
IPC分类号： H01L21/8222 , H01L27/06 , H01L29/861 , H01L29/72
CPC分类号： H01L27/0664
摘要： A semiconductor circuit includes a semiconductor layer having a surface and a monolithic output stage formed in the semiconductor layer. The monolithic output stage extends to the surface of the semiconductor layer and has a periphery within the semiconductor layer, an output terminal, and a supply terminal. A barrier well is formed in the semiconductor layer and adjacent to at least a portion of the periphery of the monolithic output stage. The barrier well extends to the surface of the semiconductor layer and has a first conductivity. A diode having first and second diode regions is disposed in the semiconductor layer. The first diode region is coupled to the supply terminal. The diode is operable to prevent current flow from the barrier well to the supply terminal when the voltage between the supply and output terminals has a first polarity.
摘要翻译：半导体电路包括具有形成在半导体层中的表面和单片输出级的半导体层。单片输出级延伸到半导体层的表面，并且在半导体层内具有周边，输出端和供电端。屏障阱形成在半导体层中并与单片输出级的周边的至少一部分相邻。势阱阱延伸到半导体层的表面并且具有第一导电性。具有第一和第二二极管区的二极管设置在半导体层中。第一二极管区域耦合到供电端子。当供电和输出端子之间的电压具有第一极性时，二极管可操作以防止电流从阻挡阱流向电源端子。

2. 发明授权

US5210481A Voltage/current characteristics control circuit particularly for protecting power transistors 失效
标题翻译：电压/电流特性控制电路特别用于保护功率晶体管
公开(公告)号：US5210481A
公开(公告)日：1993-05-11
申请号：US808484
申请日：1991-12-17
申请人： Davide Brambilla , Edoardo Botti
发明人： Davide Brambilla , Edoardo Botti
IPC分类号： G05F1/56 , H03K17/041 , H03K17/082
CPC分类号： H03K17/04113 , H03K17/0826
摘要： Voltage/current characteristics control circuit particularly for protecting power transistors, which comprises at least one power transistor; the emitter terminal of a first transistor is directly connected to the output of the power transistor; the emitter terminal of a second transistor is connected to the first terminal of the power transistor by means of a first resistor. The collector terminal and the base terminal of the first transistor are connected to a current source. The base terminal of the first transistor is connected to the base terminal of the second transistor, and the circuit furthermore comprises a protection circuitry. The circuitry is connected to the collector terminal of the second transistor through a differential stage which comprises a third transistor and a fourth transistor; the third transistor and fourth transistor have a respective second resistor and third resistor arranged in series. Divider means are furthermore provided and are interposed between the second terminal of the power transistor and the base terminals of the third transistor and fourth transistor.

3. 发明授权

US06437606B1 Method of anomalous offset detection and a corresponding circuit 有权
标题翻译：异常偏移检测方法及相应电路
公开(公告)号：US06437606B1
公开(公告)日：2002-08-20
申请号：US09687145
申请日：2000-10-13
申请人： Danilo Ranieri , Davide Brambilla , Edoardo Botti , Luca Celant
发明人： Danilo Ranieri , Davide Brambilla , Edoardo Botti , Luca Celant
IPC分类号： H03K522
CPC分类号： H03F1/52
摘要： A method of assessing the offset on the output nodes of an amplifying channel includes generating a logic signal for signaling the existence of an offset having a level exceeding a window of permitted levels symmetric about the zero level. The window is defined by a negative limit value and by a positive limit value. The method includes establishing an interval or phase of detection by applying to an input of a detection circuit a timing pulse with a certain frequency, sensing the rising edge of the timing pulse and setting a bistable circuit, and comparing the signal on the output nodes of the amplifiers channel with the window of permitted values. The bistable circuit is reset upon the occurrence, after the initial setting, of an output signal amplitude within the window of permitted values. Failure of the bistable circuit to reset before the end of the detection phase signals an excessive offset.
摘要翻译：评估放大信道的输出节点上的偏移量的方法包括：生成逻辑信号，用于发信号通知具有超过关于零电平对称的允许电平的窗口的电平的偏移的存在。窗口由负极限值和正极限值定义。该方法包括通过向检测电路的输入施加具有一定频率的定时脉冲，感测定时脉冲的上升沿并设置双稳态电路，建立检测的间隔或相位，并将输出节点上的信号进行比较放大器通道与允许值的窗口。在初始设置之后，双稳态电路在允许值的窗口内的输出信号幅度出现之后被复位。双稳态电路在检测阶段结束之前复位的故障发出过大的偏移。

4. 发明授权

US5194821A High efficiency power audio amplifiers comprising two amplifier with a single feed 失效
标题翻译：高效率功率音频放大器，包含两个放大器与单个馈电
公开(公告)号：US5194821A
公开(公告)日：1993-03-16
申请号：US793628
申请日：1991-11-18
申请人： Davide Brambilla , Guido Brasca , Edoardo Botti
发明人： Davide Brambilla , Guido Brasca , Edoardo Botti
IPC分类号： H03F1/02 , H03F3/20 , H03F3/30 , H03F3/68 , H03G3/30
CPC分类号： H03F1/0277 , H03F3/3081
摘要： The amplifier comprises a first and a second amplifier block of opposite phase driven by a single input signal and having its outputs connected to the two terminals of a load. It also comprises circuit means to disable one of the said amplifier blocks when the absolute value of the input signal is less than a predetermined threshold level. A passive feedback system capable of maintaining the amplifier gain constant is located between the aforesaid terminals of the load and the inputs to the two amplifier blocks.

5. 发明授权

US06255904B1 Anti-pop circuit for AC amplifiers 有权
标题翻译：交流放大器防爆电路
公开(公告)号：US06255904B1
公开(公告)日：2001-07-03
申请号：US09461163
申请日：1999-12-14
申请人： Giovanni Capodivacca , Davide Brambilla
发明人： Giovanni Capodivacca , Davide Brambilla
IPC分类号： H03F114
CPC分类号： H03F1/305
摘要： The anti-pop circuit includes a unity gain buffer with an input coupled to the source of the reference voltage and an output coupled to the input of the amplifier to accelerate the charging of the input coupling capacitor of the amplifier at every turn-on. The capacitor-charging buffer is automatically disabled before the turning-on of the amplifier. The charging buffer may be enabled at start up by generating an impulse of a pre-established duration at the turn-on instant by a monostable circuit or by disabling it upon verifying the decaying to zero of the charging of current of the input coupling capacitor. The circuit eliminates the popping noise at the turn-on without an excessive delay of the turning-on of the amplifier.
摘要翻译：反跳线电路包括具有耦合到参考电压源的输入的单位增益缓冲器和耦合到放大器的输入的输出，以在每次导通时加速放大器的输入耦合电容器的充电。电容充电缓冲器在放大器导通之前自动禁用。充电缓冲器可以在启动时通过在单通电路的导通瞬间产生预先建立的持续时间的脉冲，或者通过在验证输入耦合电容器的电流的衰减为零时禁用该充电缓冲器。该电路消除了导通时的爆音噪声，而放大器的导通不会过度延迟。

6. 发明授权

US07230482B2 Method of preventing abrupt voltage changes at the outputs of a pair of amplifiers and control circuit for a pair of amplifiers self-configuring in a bridge configuration 有权
标题翻译：用于在桥配置中自配置的一对放大器的一对放大器和控制电路的输出处的突变电压变化的方法
公开(公告)号：US07230482B2
公开(公告)日：2007-06-12
申请号：US11022020
申请日：2004-12-23
申请人： Fabio Chelli , Davide Brambilla
发明人： Fabio Chelli , Davide Brambilla
IPC分类号： H03F3/45 , H03F1/14 , H03F3/00
CPC分类号： H03F3/45475 , H03F1/0277 , H03F1/32 , H03F3/3081 , H03F3/68 , H03F2200/03 , H03F2200/114 , H03F2203/45138
摘要： A common mode control circuit reduces abrupt voltage changes at the outputs of a pair of amplifiers which, in turn, reduces EMI and distortions that occur when the correlation between the signals fed to the four channels of an audio system diminishes. The common mode control circuit generates for each amplifier a reference potential that is a saturated replica of the respective differential input signal of the amplifier that saturates when the amplifier switches to a bridge configuration.
摘要翻译：共模控制电路减少了一对放大器的输出端的突变电压变化，这又降低了当馈送到音频系统的四个通道的信号之间的相关性减小时发生的EMI和失真。共模控制电路为每个放大器产生作为当放大器切换到桥接配置时饱和的放大器的相应差分输入信号的饱和副本的参考电位。

7. 发明授权

US5801536A Test method for power integrated devices 失效
标题翻译：电力集成设备的测试方法
公开(公告)号：US5801536A
公开(公告)日：1998-09-01
申请号：US574616
申请日：1995-12-19
申请人： Davide Brambilla , Giovanni Capodivacca , Fabrizio Stefani
发明人： Davide Brambilla , Giovanni Capodivacca , Fabrizio Stefani
IPC分类号： G01R31/02 , G01R31/28
CPC分类号： G01R31/2853
摘要： A method of checking an integrity of an electric power connection between a contact pad of an integrated circuit and a corresponding contact pin in an electronic power device, wherein the electronic power device includes at least one final power stage powered from the respective discrete contact pad connected by means of the electric power connection to the respective contact pin. The method of checking is accomplished by providing a resistive connection between two contact pads of the electronic power device bringing the at least one final power stage, powered from the first contact pad, to a conduction state, measuring the potential difference between the two contact pins connected to the two contact pads, and comparing the potential difference with a predetermined nominal potential difference.
摘要翻译：一种检查集成电路的接触焊盘和电子功率器件中的对应接触针之间的电力连接的完整性的方法，其中所述电子功率器件包括至少一个由相应的离散接触焊盘连接的最终功率级通过与相应的接触针的电力连接。检查方法是通过在电子功率器件的两个接触焊盘之间提供电阻连接来实现的，该电阻连接引线使得从第一接触焊盘供电的至少一个最终功率级达到导通状态，测量两个接触引脚之间的电位差连接到两个接触焊盘，并将电位差与预定的标称电位差进行比较。

8. 发明申请

US20050174705A1 Method for preventing cross-conductions and interactions between supply lines of a device and a circuit for limiting the voltage difference between two regulated output voltages 审中-公开
标题翻译：用于防止器件的电源线与用于限制两个稳定输出电压之间的电压差的电路的交叉传导和相互作用的方法
公开(公告)号：US20050174705A1
公开(公告)日：2005-08-11
申请号：US11056407
申请日：2005-02-11
申请人： Davide Brambilla , Daniela Nebuloni
发明人： Davide Brambilla , Daniela Nebuloni
IPC分类号： G05F1/56 , H02H7/00
CPC分类号： G05F1/56
摘要： In a device that includes a pair of closed-loop voltage regulators each including an input transconductance stage receiving a reference voltage and a feedback voltage, an intermediate transresistance stage, an output buffer operatively in cascade for generating on an output node the regulated output voltage and negative feedback means for providing the feedback voltage to the input stage, the method includes a circuit that limits the difference between two output regulated voltages. The limiting circuit includes a differential transconductance amplifier input with voltages proportional to the output voltages of the regulators or obtained by adding an offset voltage to the output voltage of the regulators for injecting in, or draining from, an input node of the intermediate stage of one of the regulators, a current as a function of the relative unbalance of the differential transconductance amplifier.
摘要翻译：在包括一对闭合电压调节器的装置中，每一个包括接收参考电压和反馈电压的输入跨导级，中间跨阻级，可级联的输出缓冲器，用于在输出节点上产生调节的输出电压，以及负反馈装置用于向输入级提供反馈电压，该方法包括限制两个输出调节电压之间的差的电路。限制电路包括差分跨导放大器输入，其具有与调节器的输出电压成比例的电压，或者通过将偏移电压加到调节器的输出电压上，以将其输入或从其中间级的输入节点排出的调节器，作为差分跨导放大器的相对不平衡的函数的电流。

9. 发明授权

US5874852A Current generator circuit having a wide frequency response 失效
标题翻译：电流发生器电路具有较宽的频率响应
公开(公告)号：US5874852A
公开(公告)日：1999-02-23
申请号：US706068
申请日：1996-08-30
申请人： Davide Brambilla , Daniela Nebuloni , Giorgio Rossi , Sergio Lecce
发明人： Davide Brambilla , Daniela Nebuloni , Giorgio Rossi , Sergio Lecce
IPC分类号： G05F3/26 , H03F3/345 , H03F3/343
CPC分类号： H03F3/345 , G05F3/267
摘要： A current generator circuit with controllable frequency response has at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (I.sub.out) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg by an impedance matching circuit configured to hold the same voltage value at both terminals (Ga1 and Ga2). The impedance matching circuit has an adjustable output impedance, specifically lower in value than the value to be had without this circuit. It functions to regulate the impedance on the control node (Ga2) of the second transistor (M2). The invention is equally applicable to N-channel and P-channel MOS transistors. Advantageously, the reference current can be varied by an external signal which is a function of the output signal, to provide feedback regulating features.
摘要翻译：具有可控频率响应的电流发生器电路具有由MOS晶体管形成的至少一个电流镜，其通过保持在恒定电压的端子供电，具有输入支路，参考电流（I1）由第一电流发生器 G1），并且具有用于在镜的输出端（OUT）上产生与参考电流（I1）成比例的镜像电流（Iout）的输出支路。输入支路至少包括二极管连接的第一晶体管（M1），并且具有通过阻抗匹配电路耦合到包括在输出支路中的第二晶体管（M2）的对应端子（Ga2）的控制端子（Ga1）被配置为在两个端子（Ga1和Ga2）处保持相同的电压值。阻抗匹配电路具有可调节的输出阻抗，具体值低于没有该电路的值。它用于调节第二晶体管（M2）的控制节点（Ga2）上的阻抗。本发明同样适用于N沟道和P沟道MOS晶体管。有利地，参考电流可以通过作为输出信号的函数的外部信号来改变，以提供反馈调节特征。

10. 发明授权

US5204638A Intrinsic offset recovery circuit particularly for amplifiers 失效
标题翻译：内置偏移电路，特别适用于放大器
公开(公告)号：US5204638A
公开(公告)日：1993-04-20
申请号：US808492
申请日：1991-12-17
申请人： Davide Brambilla , Fabrizio Stefani
发明人： Davide Brambilla , Fabrizio Stefani
IPC分类号： H03F3/34 , H03F3/343 , H03F3/45
CPC分类号： H03F3/45479 , H03F3/3437
摘要： Intrinsic offset recovery circuit particularly for amplifiers, which comprises an input differential amplifier constituted by a first PNP transistor, by a second PNP transistor, by a third NPN transistor, by a fourth NPN transistor and by a first constant-current source, and a unitary-gain output stage. The recovery circuit furthermore comprises, as connection between the input differential amplifier and the unitary-gain output stage, a gain stage which comprises a fifth NPN transistor which is connected to the output of the input differential amplifier and is connected to a sixth NPN transistor and to a seventh PNP transistor. The seventh transistor is connected to the sixth transistor. The seventh transistor and the sixth transistor are connected to the unitary-gain output stage.

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