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1. 发明授权

US08288244B2 Lateral passive device having dual annular electrodes 有权
标题翻译：具有双环形电极的横向无源器件
公开(公告)号：US08288244B2
公开(公告)日：2012-10-16
申请号：US12835283
申请日：2010-07-13
申请人： David S. Collins , Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： David S. Collins , Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L21/76 , H01L29/00
CPC分类号： H01L29/8611 , H01L27/0814 , H01L29/417 , H01L29/868 , H01L29/872 , H01L29/93
摘要： A method for forming a lateral passive device including a dual annular electrode is disclosed. The annular electrodes formed from the method include an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate (substrate) is greatly reduced.
摘要翻译：公开了一种用于形成包括双环形电极的横向无源器件的方法。由该方法形成的环形电极包括阳极和阴极。环形电极允许将阳极和阴极串联电阻优化为固定装置区域的最低值。此外，对底板（衬底）的寄生电容大大降低。

2. 发明申请

US20100279483A1 LATERAL PASSIVE DEVICE HAVING DUAL ANNULAR ELECTRODES 有权
标题翻译：具有双重电极的侧向被动装置
公开(公告)号：US20100279483A1
公开(公告)日：2010-11-04
申请号：US12835283
申请日：2010-07-13
申请人： David S. Collins , Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： David S. Collins , Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L21/329 , H01L21/04
CPC分类号： H01L29/8611 , H01L27/0814 , H01L29/417 , H01L29/868 , H01L29/872 , H01L29/93
摘要： A lateral passive device is disclosed including a dual annular electrode. The annular electrodes form an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate (substrate) is greatly reduced. In one embodiment, a device includes a first annular electrode surrounding a second annular electrode formed on a substrate, and the second annular electrode surrounds an insulator region. A related method is also disclosed.
摘要翻译：公开了一种包括双环形电极的横向无源器件。环形电极形成阳极和阴极。环形电极允许将阳极和阴极串联电阻优化为固定装置区域的最低值。此外，对底板（衬底）的寄生电容大大降低。在一个实施例中，装置包括围绕形成在基板上的第二环形电极的第一环形电极，并且第二环形电极围绕绝缘体区域。还公开了相关方法。

3. 发明申请

US20070278614A1 LATERAL PASSIVE DEVICE HAVING DUAL ANNULAR ELECTRODES 失效
标题翻译：具有双重电极的侧向被动装置
公开(公告)号：US20070278614A1
公开(公告)日：2007-12-06
申请号：US11422125
申请日：2006-06-05
申请人： David S. Collins , Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： David S. Collins , Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L29/00
CPC分类号： H01L29/8611 , H01L27/0814 , H01L29/417 , H01L29/868 , H01L29/872 , H01L29/93
摘要： A lateral passive device is disclosed including a dual annular electrode. The annular electrodes form an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate (substrate) is greatly reduced. In one embodiment, a device includes a first annular electrode surrounding a second annular electrode formed on a substrate, and the second annular electrode surrounds an insulator region. A related method is also disclosed.
摘要翻译：公开了一种包括双环形电极的横向无源器件。环形电极形成阳极和阴极。环形电极允许将阳极和阴极串联电阻优化为固定装置区域的最低值。此外，对底板（衬底）的寄生电容大大降低。在一个实施例中，装置包括围绕形成在基板上的第二环形电极的第一环形电极，并且第二环形电极围绕绝缘体区域。还公开了相关方法。

4. 发明授权

US07821097B2 Lateral passive device having dual annular electrodes 失效
标题翻译：具有双环形电极的横向无源器件
公开(公告)号：US07821097B2
公开(公告)日：2010-10-26
申请号：US11422125
申请日：2006-06-05
申请人： David S. Collins , Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： David S. Collins , Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L29/00
CPC分类号： H01L29/8611 , H01L27/0814 , H01L29/417 , H01L29/868 , H01L29/872 , H01L29/93
摘要： A lateral passive device is disclosed including a dual annular electrode. The annular electrodes form an anode and a cathode. The annular electrodes allow anode and cathode series resistances to be optimized to the lowest values at a fixed device area. In addition, the parasitic capacitance to a bottom plate (substrate) is greatly reduced. In one embodiment, a device includes a first annular electrode surrounding a second annular electrode formed on a substrate, and the second annular electrode surrounds an insulator region. A related method is also disclosed.
摘要翻译：公开了一种包括双环形电极的横向无源器件。环形电极形成阳极和阴极。环形电极允许将阳极和阴极串联电阻优化为固定装置区域的最低值。此外，对底板（衬底）的寄生电容大大降低。在一个实施例中，装置包括围绕形成在基板上的第二环形电极的第一环形电极，并且第二环形电极围绕绝缘体区域。还公开了相关方法。

5. 发明授权

US08338265B2 Silicided trench contact to buried conductive layer 失效
标题翻译：硅化沟槽接触埋入导电层
公开(公告)号：US08338265B2
公开(公告)日：2012-12-25
申请号：US12269069
申请日：2008-11-12
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L21/76
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译：沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。沟槽随后填充有中间线（MOL）电介质。可以在沟槽接触硅化物上形成接触通孔。沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

6. 发明申请

US20100117237A1 Silicided Trench Contact to Buried Conductive Layer 失效
标题翻译：硅胶沟与埋地导电层接触
公开(公告)号：US20100117237A1
公开(公告)日：2010-05-13
申请号：US12269069
申请日：2008-11-12
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L23/52 , H01L21/02
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译：沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。沟槽随后填充有中间线（MOL）电介质。可以在沟槽接触硅化物上形成接触通孔。沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

7. 发明申请

US20140239498A1 SILICIDED TRENCH CONTACT TO BURIED CONDUCTIVE LAYER 审中-公开
标题翻译：硅胶触点接触到导电层
公开(公告)号：US20140239498A1
公开(公告)日：2014-08-28
申请号：US13570737
申请日：2012-08-09
申请人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
发明人： Douglas D. Coolbaugh , Jeffrey B. Johnson , Peter J. Lindgren , Xuefeng Liu , James S. Nakos , Bradley A. Orner , Robert M. Rassel , David C. Sheridan
IPC分类号： H01L23/48 , H01L23/482
CPC分类号： H01L21/743 , H01L21/28518 , H01L21/76224 , H01L21/8249 , H01L27/0623 , H01L29/41 , H01L2924/0002 , H01L2924/00
摘要： A trench contact silicide is formed on an inner wall of a contact trench that reaches to a buried conductive layer in a semiconductor substrate to reduce parasitic resistance of a reachthrough structure. The trench contact silicide is formed at the bottom, on the sidewalls of the trench, and on a portion of the top surface of the semiconductor substrate. The trench is subsequently filled with a middle-of-line (MOL) dielectric. A contact via may be formed on the trench contact silicide. The trench contact silicide may be formed through a single silicidation reaction with a metal layer or through multiple silicidation reactions with multiple metal layers.
摘要翻译：沟槽接触硅化物形成在接触沟槽的内壁上，该接触沟槽的内壁到达半导体衬底中的掩埋导电层，以减小通孔结构的寄生电阻。沟槽接触硅化物形成在底部，沟槽的侧壁上以及在半导体衬底的顶表面的一部分上。沟槽随后填充有中间线（MOL）电介质。可以在沟槽接触硅化物上形成接触通孔。沟槽接触硅化物可以通过与金属层的单一硅化反应或通过与多个金属层的多次硅化反应形成。

8. 发明授权

US08592293B2 Schottky barrier diodes for millimeter wave SiGe BiCMOS applications 有权
标题翻译：用于毫米波SiGe BiCMOS应用的肖特基势垒二极管
公开(公告)号：US08592293B2
公开(公告)日：2013-11-26
申请号：US13028673
申请日：2011-02-16
申请人： Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel
发明人： Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel
IPC分类号： H01L21/28
CPC分类号： H01L29/872 , H01L21/8249 , H01L27/0635 , H01L27/0814 , H01L29/161 , H01L29/47 , H01L29/66143
摘要： A method for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.
摘要翻译：一种在SiGe BiCMOS晶片上形成肖特基势垒二极管的方法，包括形成提供高于约1.0THz的截止频率（Fc）的结构。在实施例中，提供高于约1.0THz的截止频率（Fc）的结构可以包括具有提供高于约1.0THz的截止频率（FC）的阳极区域的阳极，具有提供截止频率频率（FC）高于约1.0THz，在提供高于约1.0THz的截止频率（FC）的能量和剂量下的p型防护，所述p型护罩具有提供高于约截止频率（FC）的尺寸 1.0 THz，以及具有n型掺杂剂的良好裁缝，其提供高于约1.0THz的截止频率（FC）。

9. 发明授权

US07936041B2 Schottky barrier diodes for millimeter wave SiGe BICMOS applications 有权
标题翻译：用于毫米波SiGe BICMOS应用的肖特基势垒二极管
公开(公告)号：US07936041B2
公开(公告)日：2011-05-03
申请号：US11853973
申请日：2007-09-12
申请人： Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel
发明人： Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L21/8249 , H01L27/0635 , H01L27/0814 , H01L29/161 , H01L29/47 , H01L29/66143
摘要： The structure for millimeter-wave frequency applications, includes a Schottky barrier diode (SBD) with a cutoff frequency (FC) above 1.0 THz formed on a SiGe BiCMOS wafer. A method is also contemplated for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.
摘要翻译：毫米波频率应用的结构包括在SiGe BiCMOS晶片上形成的截止频率（FC）大于1.0THz的肖特基势垒二极管（SBD）。还考虑了在SiGe BiCMOS晶片上形成肖特基势垒二极管的方法，包括形成提供高于约1.0THz的截止频率（Fc）的结构。在实施例中，提供高于约1.0THz的截止频率（Fc）的结构可以包括具有提供高于约1.0THz的截止频率（FC）的阳极区域的阳极，具有提供截止频率频率（FC）高于约1.0THz，在提供高于约1.0THz的截止频率（FC）的能量和剂量下的p型防护，所述p型护罩具有提供高于约截止频率（FC）的尺寸 1.0 THz，以及具有n型掺杂剂的良好裁缝，其提供高于约1.0THz的截止频率（FC）。

10. 发明申请

US20080179703A1 SCHOTTKY BARRIER DIODES FOR MILLIMETER WAVE SiGe BICMOS APPLICATIONS 有权
标题翻译：肖特基二极管适用于千兆波SiGe BICMOS应用
公开(公告)号：US20080179703A1
公开(公告)日：2008-07-31
申请号：US11853973
申请日：2007-09-12
申请人： Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel
发明人： Jeffrey B. Johnson , Xuefeng Liu , Bradley A. Orner , Robert M. Rassel
IPC分类号： H01L29/872 , H01L21/329
CPC分类号： H01L29/872 , H01L21/8249 , H01L27/0635 , H01L27/0814 , H01L29/161 , H01L29/47 , H01L29/66143
摘要： The structure for millimeter-wave frequency applications, includes a Schottky barrier diode (SBD) with a cutoff frequency (FC) above 1.0 THz formed on a SiGe BiCMOS wafer. A method is also contemplated for forming a Schottky barrier diode on a SiGe BiCMOS wafer, including forming a structure which provides a cutoff frequency (Fc) above about 1.0 THz. In embodiments, the structure which provides a cutoff frequency (Fc) above about 1.0 THz may include an anode having an anode area which provides a cutoff frequency (FC) above about 1.0 THz, an n-epitaxial layer having a thickness which provides a cutoff frequency (FC) above about 1.0 THz, a p-type guardring at an energy and dosage which provides a cutoff frequency (FC) above about 1.0 THz, the p-type guardring having a dimension which provides a cutoff frequency (FC) above about 1.0 THz, and a well tailor with an n-type dopant which provides a cutoff frequency (FC) above about 1.0 THz.
摘要翻译：毫米波频率应用的结构包括在SiGe BiCMOS晶片上形成的截止频率（F SUB）高于1.0THz的肖特基势垒二极管（SBD）。还考虑了在SiGe BiCMOS晶片上形成肖特基势垒二极管的方法，包括形成提供高于约1.0THz的截止频率（F SUB）的结构。在实施例中，提供约1.0THz以上的截止频率（F SUB）的结构可以包括具有提供上述截止频率（F SUB C）的阳极区域的阳极约1.0THz，具有提供高于约1.0THz的截止频率（F SUB）的厚度的n外延层，以能量和剂量提供截止频率（F）的p型防护在约1.0THz以上的p型防护装置，具有提供高于约1.0THz的截止频率（F SUB C）的尺寸，以及具有n 型掺杂剂，其在约1.0THz以上提供截止频率（F C C）。

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