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1. 发明授权

US08799346B2 Belief propagation processor 有权
标题翻译：信仰传播处理器
公开(公告)号：US08799346B2
公开(公告)日：2014-08-05
申请号：US13079204
申请日：2011-04-04
申请人： David Reynolds , Benjamin Vigoda
发明人： David Reynolds , Benjamin Vigoda
IPC分类号： G06G7/00
CPC分类号： H03M13/1111 , G06G7/122 , G06G7/1942 , H03M13/1137 , H03M13/1188 , H03M13/6597
摘要： A processor includes a first memory module for storing a first set of storage values each representing a respective input, and a second memory module for storing a second set of storage values in analog form. An analog module is coupled to the first and the second memory modules. The analog module is configured to, in each operation cycle of at least one iteration, update at least some of the second set of storage values based on the first and the second sets of storage values. An output module is for generating a set of outputs from at least some of the second set of storage values.
摘要翻译：处理器包括：第一存储器模块，用于存储每个表示相应输入的第一组存储值;以及第二存储器模块，用于以模拟形式存储第二组存储值。模拟模块耦合到第一和第二存储器模块。模拟模块被配置为在至少一次迭代的每个操作周期中，基于第一和第二组存储值来更新第二组存储值中的至少一些。输出模块用于从第二组存储值中的至少一些产生一组输出。

2. 发明授权

US08792602B2 Mixed signal stochastic belief propagation 有权
标题翻译：混合信号随机信念传播
公开(公告)号：US08792602B2
公开(公告)日：2014-07-29
申请号：US13032520
申请日：2011-02-22
申请人： Jeffrey Bernstein , Benjamin Vigoda , David Reynolds , Alexander Alexeyev , William Bradley
发明人： Jeffrey Bernstein , Benjamin Vigoda , David Reynolds , Alexander Alexeyev , William Bradley
IPC分类号： H04L7/00 , H03M13/11 , H03M13/00
CPC分类号： H03M13/6597 , H03M13/1111
摘要： A processor implements a network of functional nodes and communication paths between the nodes. The processor includes a plurality of circuit implementations of the functional nodes of the processor; and a plurality of signal paths implementing the communication paths linking the circuit implementations of the nodes. At least some of the signal paths are configured to pass signal values represented according to temporal patterns of signal levels on the signal paths. The processor also includes a plurality of circuit components for conversion between a signal value represented as a signal level (e.g., voltage or current level) and a signal value represented as a temporal pattern.
摘要翻译：处理器实现节点之间的功能节点和通信路径的网络。处理器包括处理器的功能节点的多个电路实现; 以及实现链接节点的电路实现的通信路径的多个信号路径。至少一些信号路径被配置为传递根据信号路径上的信号电平的时间模式表示的信号值。处理器还包括用于在表示为信号电平（例如，电压或电流电平）的信号值和表示为时间模式的信号值之间进行转换的多个电路部件。

3. 发明申请

US20130094298A1 STORAGE DEVICES WITH SOFT PROCESSING 有权
标题翻译：具有软处理的存储设备
公开(公告)号：US20130094298A1
公开(公告)日：2013-04-18
申请号：US13471816
申请日：2012-05-15
申请人： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Ziatkovic
发明人： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Ziatkovic
IPC分类号： G11C7/00 , G11C16/04 , G11C11/24
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
摘要： A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
摘要翻译：存储装置包括具有一组存储元件的存储阵列。每个存储元件可以写入一组离散的物理状态。读取电路选择一个或多个存储元件，并为每个选定的存储元件生成表示所选存储元件的物理状态的模拟信号。信号处理电路处理模拟信号以产生多个输出，其中每个输出表示所选择的存储元件与离散的物理状态集合中的一个或多个的不同子集的关联程度。

4. 发明申请

US20100246289A1 STORAGE DEVICES WITH SOFT PROCESSING 有权
公开(公告)号：US20100246289A1
公开(公告)日：2010-09-30
申请号：US12537081
申请日：2009-08-06
申请人： Benjamin Vigoda , Jeffrey Bernstein , Jeffrey Venuti , David Reynolds , Alexander Alexeyev
发明人： Benjamin Vigoda , Jeffrey Bernstein , Jeffrey Venuti , David Reynolds , Alexander Alexeyev
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
摘要： A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

5. 发明授权

US08717818B1 Storage device architecture 有权
标题翻译：存储设备架构
公开(公告)号：US08717818B1
公开(公告)日：2014-05-06
申请号：US13292427
申请日：2011-11-09
申请人： Benjamin Vigoda , David Reynolds
发明人： Benjamin Vigoda , David Reynolds
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/28 , G11C11/5642 , G11C16/0483 , G11C2029/0411
摘要： In one aspect, a storage device includes a plurality of storage strings, each comprising a serial interconnection of a plurality of active storage elements, each storage element having a part for maintaining a storage state and a part of modulating a current through the element according to the storage state. The device also includes mapping circuitry for selectively sensing a storage state of a storage element in a storage string by forming current though the storage element that is a non-linear function of the storage state. In some examples, the mapping circuitry comprises reference string of active elements, and the mapping circuitry selectively senses a storage state by forming a difference in currents in the sensed storage string and in the reference string that is a non-linear function of the storage state. In some examples, the active storage elements comprise floating gate transistors.
摘要翻译：在一个方面，一种存储设备包括多个存储串，每个存储串包括多个有源存储元件的串行互连，每个存储元件具有用于保持存储状态的部分，以及调制根据该元件的电流的一部分存储状态。该装置还包括映射电路，用于通过形成电流，通过作为存储状态的非线性函数的存储元件来选择性地感测存储串中的存储元件的存储状态。在一些示例中，映射电路包括有源元件的参考串，并且映射电路通过形成感测存储串中的电流差和在作为存储状态的非线性函数的参考串中选择性地感测存储状态。在一些示例中，有源存储元件包括浮置栅极晶体管。

6. 发明授权

US08179731B2 Storage devices with soft processing 有权
公开(公告)号：US08179731B2
公开(公告)日：2012-05-15
申请号：US12537045
申请日：2009-08-06
申请人： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Zlatkovic
发明人： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Zlatkovic
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
摘要： A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

7. 发明授权

US08107306B2 Storage devices with soft processing 有权
标题翻译：软处理存储设备
公开(公告)号：US08107306B2
公开(公告)日：2012-01-31
申请号：US12537081
申请日：2009-08-06
申请人： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Zlatkovic
发明人： Benjamin Vigoda , Eric Nestler , Jeffrey Bernstein , David Reynolds , Alexander Alexeyev , Jeffrey Venuti , William Bradley , Vladimir Zlatkovic
IPC分类号： G11C7/00
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
摘要： A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
摘要翻译：存储装置包括具有一组存储元件的存储阵列。每个存储元件可以写入一组离散的物理状态。读取电路选择一个或多个存储元件，并为每个选定的存储元件生成表示所选存储元件的物理状态的模拟信号。信号处理电路处理模拟信号以产生多个输出，其中每个输出表示所选择的存储元件与离散的物理状态集合中的一个或多个的不同子集的关联程度。

8. 发明申请

US20110255612A1 MIXED SIGNAL STOCHASTIC BELIEF PROPAGATION 有权
标题翻译：混合信号STOCHASTIC BELIEF传播
公开(公告)号：US20110255612A1
公开(公告)日：2011-10-20
申请号：US13032520
申请日：2011-02-22
申请人： Jeffrey Bernstein , Benjamin Vigoda , David Reynolds , Alexander Alexeyev , William Bradley
发明人： Jeffrey Bernstein , Benjamin Vigoda , David Reynolds , Alexander Alexeyev , William Bradley
IPC分类号： H04L27/00
CPC分类号： H03M13/6597 , H03M13/1111
摘要： A processor implements a network of functional nodes and communication paths between the nodes. The processor includes a plurality of circuit implementations of the functional nodes of the processor; and a plurality of signal paths implementing the communication paths linking the circuit implementations of the nodes. At least some of the signal paths are configured to pass signal values represented according to temporal patterns of signal levels on the signal paths. The processor also includes a plurality of circuit components for conversion between a signal value represented as a signal level (e.g., voltage or current level) and a signal value represented as a temporal pattern.
摘要翻译：处理器实现节点之间的功能节点和通信路径的网络。处理器包括处理器的功能节点的多个电路实现; 以及实现链接节点的电路实现的通信路径的多个信号路径。至少一些信号路径被配置为传递根据信号路径上的信号电平的时间模式表示的信号值。处理器还包括用于在表示为信号电平（例如，电压或电流电平）的信号值和表示为时间模式的信号值之间进行转换的多个电路部件。

9. 发明申请

US20100246287A1 STORAGE DEVICES WITH SOFT PROCESSING 有权
标题翻译：具有软处理的存储设备
公开(公告)号：US20100246287A1
公开(公告)日：2010-09-30
申请号：US12537045
申请日：2009-08-06
申请人： Benjamin Vigoda , Jeffrey Bernstein , Jeffrey Venuti , David Reynolds , Alexander Alexeyev
发明人： Benjamin Vigoda , Jeffrey Bernstein , Jeffrey Venuti , David Reynolds , Alexander Alexeyev
IPC分类号： G11C7/16 , G11C7/00
CPC分类号： G11C7/00 , G11C7/1006 , G11C7/16 , G11C11/24 , G11C11/5642 , G11C16/04 , G11C27/005 , G11C29/00
摘要： A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.
摘要翻译：存储装置包括具有一组存储元件的存储阵列。每个存储元件可以写入一组离散的物理状态。读取电路选择一个或多个存储元件，并为每个选定的存储元件生成表示所选存储元件的物理状态的模拟信号。信号处理电路处理模拟信号以产生多个输出，其中每个输出表示所选择的存储元件与离散的物理状态集合中的一个或多个的不同子集的关联程度。

10. 发明授权

US09048830B2 Circuits for soft logical functions 有权
标题翻译：用于软逻辑功能的电路
公开(公告)号：US09048830B2
公开(公告)日：2015-06-02
申请号：US12716150
申请日：2010-03-02
申请人： David Reynolds , Benjamin Vigoda
发明人： David Reynolds , Benjamin Vigoda
IPC分类号： G11C7/00 , H03K19/094 , G06N7/00 , G11C11/56 , G11C16/28 , H03K19/21
CPC分类号： H03K19/09432 , G06N7/005 , G11C11/5642 , G11C16/28 , H03K19/21
摘要： A circuit implementing a soft logical processing network includes an interconnection of analog processing elements, which can include soft logic gates, for instance soft Equals gates and soft XOR gates. In some examples, each of the soft logic gates include multiple circuit parts, with each part including an input configured to accept a voltage signal representation of a soft logical quantity, and a conversion section configured to use the accepted voltage representation to form a corresponding current signal. The current signals are combined to form a signal representation of the output of the gate. In an application of soft logic gates, a memory includes a group of electrical storage elements, each electrical storage elements carrying a respective storage values; a group of conversion elements, each conversion element being coupled to a respective electrical storage element for selectively converting the corresponding storage value to a current signal; and a current combination element for combining the current signals to form an output signal.
摘要翻译：实现软逻辑处理网络的电路包括模拟处理元件的互连，其可以包括软逻辑门，例如软等于门和软XOR门。在一些示例中，每个软逻辑门包括多个电路部分，每个部分包括被配置为接受软逻辑量的电压信号表示的输入，以及被配置为使用所接受的电压表示形成对应的电流信号。电流信号被组合以形成门的输出的信号表示。在软逻辑门的应用中，存储器包括一组电存储元件，每个电存储元件承载相应的存储值; 一组转换元件，每个转换元件耦合到相应的电存储元件，用于选择性地将相应的存储值转换为电流信号; 以及用于组合电流信号以形成输出信号的当前组合元件。

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