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1. 发明授权

US06766460B1 System and method for power management in a Java accelerator environment 有权
标题翻译：用于Java加速器环境中的电源管理的系统和方法
公开(公告)号：US06766460B1
公开(公告)日：2004-07-20
申请号：US09645468
申请日：2000-08-23
申请人： David R. Evoy , Lonnie C. Goff , Bonnie Sexton
发明人： David R. Evoy , Lonnie C. Goff , Bonnie Sexton
IPC分类号： G06F128
CPC分类号： G06F9/3879 , G06F1/3203
摘要： A power management method is disclosed which provides power management for a hardware based Java accelerator. Initially, a Java mode signal is provided from a host processor in response to initiating a Java application. Thereafter, power to the host processor is reduced, and power to a Java processor is increased in response to the Java mode signal. Then, when execution of the Java application halts, a Java completion signal is generated from the Java processor, thus signaling the system to return control back to the host processor.
摘要翻译：公开了一种为基于硬件的Java加速器提供功率管理的功率管理方法。最初，响应于启动Java应用程序，从主机处理器提供Java模式信号。此后，减少了对主处理器的电力，并且响应于Java模式信号而增加了对Java处理器的供电。然后，当Java应用程序的执行停止时，从Java处理器生成Java完成信号，从而发信号通知系统将控制返回到主机处理器。

2. 发明授权

US10209957B2 Partial remainder/divisor table split implementation 有权
公开(公告)号：US10209957B2
公开(公告)日：2019-02-19
申请号：US14972077
申请日：2015-12-16
申请人： Bonnie Sexton
发明人： Bonnie Sexton
IPC分类号： G06F7/46 , G06F7/537 , G06F7/552 , G06F7/72
摘要： According to one general aspect, an apparatus may include a key selector configured to select a personality key from at least a portion of an input value. The apparatus may include a sparse look-up table configured to determine a portion of a result based upon the personality key and a prior remainder. The apparatus may include an adder configured to compute a current remainder based upon, at least, the input value, and the portion of the result. The apparatus may be configured to iteratively compute current remainders and portions of the result until either the current remainder is zero, or a predefined level of precision is reached.

3. 发明申请

US20060198524A1 Hardware implementation of the mixcolumn/invmiscolumn functions 审中-公开
标题翻译： mixcolumn / invmiscolumn函数的硬件实现
公开(公告)号：US20060198524A1
公开(公告)日：2006-09-07
申请号：US10556329
申请日：2004-05-10
申请人： Bonnie Sexton
发明人： Bonnie Sexton
IPC分类号： H04L9/00
CPC分类号： H04L9/0631 , H04L2209/122 , H04L2209/125 , H04L2209/80
摘要： An encryption/decryption unit, a conversion module, a method and a computer program product share common logic for both a cipher transformation and an inverse cipher transformation to reduce the number of gates requires with a small increase in wait time. A keyschedule unit providing at least one key value. The conversion module, which is in communication with the keyschedule unit, converts a block of plain text/ciphered text into a predetermined number of byte units in a first plurality of columns. The conversion module includes a MixColumnAll submodule that utilizes shared circuitry for both a transformation of a cipher function to produce a second plurality of columns from the first plurality of columns, and for an inverse cipher function to produce the first plurality of columns from the second plurality of columns. The MixColumnAll submodule performs a combined MixColumn and InvMixColumn that are performed in AES. A block round unit for encrypting/decrypting the predetermined number of byte units into ciphered text/plain text.
摘要翻译：加密/解密单元，转换模块，方法和计算机程序产品共享用于密码变换和逆密码变换的公共逻辑以减少门数需要等待时间的小的增加。提供至少一个键值的键调度单元。与密钥调度单元通信的转换模块将明文/加密文本块在第一多个列中转换成预定数量的字节单位。该转换模块包括一个MixColumnAll子模块，它利用共享电路来进行加密函数的变换以从第一多个列产生第二多个列，以及使用反向密码函数从第二多个列产生第一多个列的列。 MixColumnAll子模块执行AES中执行的组合MixColumn和InvMixColumn。用于将预定数量的字节单元加密/解密为加密文本/纯文本的块循环单元。

4. 发明申请

US20070174379A1 Pre-saturating fixed-point multiplier 有权
标题翻译：预饱和定点乘数
公开(公告)号：US20070174379A1
公开(公告)日：2007-07-26
申请号：US11336358
申请日：2006-01-20
申请人： Kenneth Dockser , Bonnie Sexton
发明人： Kenneth Dockser , Bonnie Sexton
IPC分类号： G06F7/52
CPC分类号： G06F7/49921 , G06F7/5338
摘要： A pre-saturating multiplier inspects the operands to a multiply operation prior to performing any multiplication. If the operands will cause an overflow requiring saturation, the multiplier outputs the saturated value without multiplying the original operands. In one embodiment, parameters derived from the operands are altered such that when the multiply operation is performed on the altered parameters, the multiplier produces the saturated result. This may comprise altering a Booth recoded bit group to select a negative zero instead of a zero as a partial product, and suppressing the addition of the value one to the partial products (thus effectively subtracting the value one). In another embodiment, when the operands that will cause an overflow are detected, the output of the multiplier is forced to a predetermined saturation value.
摘要翻译：预饱和乘法器在执行任何乘法之前检查操作数到乘法运算。如果操作数将导致需要饱和的溢出，则乘法器输出饱和值，而不会将原始操作数相乘。在一个实施例中，改变从操作数导出的参数，使得当对改变的参数执行乘法运算时，乘法器产生饱和结果。这可以包括改变布斯重新编码的位组，以选择负零而不是零作为部分乘积，并且抑制将值1加到部分积（从而有效地减去值1）。在另一个实施例中，当检测到将导致溢出的操作数时，乘法器的输出被强制为预定的饱和值。

5. 发明申请

US20060109981A1 Small hardware implementation of the subbyte function of rijndael 失效
标题翻译：小硬件实现了rijndael的子字节功能
公开(公告)号：US20060109981A1
公开(公告)日：2006-05-25
申请号：US10538556
申请日：2003-11-28
申请人： Bonnie Sexton
发明人： Bonnie Sexton
IPC分类号： H04L9/28
CPC分类号： H04L9/0631 , H04L2209/122 , H04L2209/125
摘要： A small hardware implementation is provided for the Advanced Encryption Standard SubByte function that implements the affine transform and inverse transform in a single Affine-All transform using a multiplicative inverse ROM. The logic is greatly reduced and the maximum path delay is reduced compared to a multiplexor implementation and is slightly greater than a ROM implementation.
摘要翻译：为使用乘法反向ROM的单一仿射全变换中实现仿射变换和逆变换的高级加密标准子字节功能提供了小的硬件实现。与多路复用器实现相比，逻辑被大大减少并且最大路径延迟减小并且略大于ROM实现。

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