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1. 发明授权

US5157395A Variable decimation architecture for a delta-sigma analog-to-digital converter 失效
标题翻译： DELTA-SIGMA模拟数字转换器的可变分频结构
公开(公告)号：US5157395A
公开(公告)日：1992-10-20
申请号：US664034
申请日：1991-03-04
申请人： Bruce Del Signore , Eric J. Swanson , Jeffrey M. Klaas , David L. Medlock
发明人： Bruce Del Signore , Eric J. Swanson , Jeffrey M. Klaas , David L. Medlock
IPC分类号： H03H17/02 , H03H17/06
CPC分类号： H03H17/0294 , H03H17/0664
摘要： An analog-to-digital converter includes a delta-sigma modulator (10), having the output thereof filtered by a digital filter section. The digital filter section includes a first fixed decimation filter (12) followed by a variable decimation filter section (14) and an output low-pass filter section (16), having a fixed decimation ratio. The fixed variable decimation filter section (14) includes a single FIR filter (24) that has data processed therethrough with different sampling rates. A recursive controller (26) receives an external configuration input to determine the number of passes through the filter (24) that are required to provide the desired decimation ratio.
摘要翻译：模数转换器包括Δ-Σ调制器（10），其输出被数字滤波器部分滤波。数字滤波器部分包括具有固定抽取比率的第一固定抽取滤波器（12）和随后的可变抽取滤波器部分（14）和输出低通滤波器部分（16）。固定可变抽取滤波器部分（14）包括具有不同采样率的处理数据的单个FIR滤波器（24）。递归控制器（26）接收外部配置输入以确定提供所需抽取比所需的通过过滤器（24）的通过次数。

2. 发明授权

US5608676A Current limited current reference for non-volatile memory sensing 失效
标题翻译：用于非易失性存储器感应的电流限制电流参考
公开(公告)号：US5608676A
公开(公告)日：1997-03-04
申请号：US114478
申请日：1993-08-31
申请人： David L. Medlock , Eric J. Swanson
发明人： David L. Medlock , Eric J. Swanson
IPC分类号： G11C16/04 , G11C16/24 , G11C16/28 , G11C7/00
CPC分类号： G11C16/28 , G11C16/0433 , G11C16/24
摘要： A non-volatile memo includes the reference cells programmed to opposite logic states whose outputs are combined and then equally divided to provide a reference signal to a sense amplifier which is one half of the sum of the signals from a high conductivity data cell and a low conductivity data cell. The non-volatile memory also includes a bias voltage generator which uses a high conductivity non-volatile reference cell for a reference, and which produces a bias voltage which is coupled to current limiting transistors at the inputs of the sense amplifier so that the current into the sense amplifier is limited and therefore limits the power used by the non-volatile memory.
摘要翻译：非易失性备忘录包括被编程为相反逻辑状态的参考单元，其输出被组合，然后被均分，以将参考信号提供给读出放大器，该读出放大器是来自高电导率数据单元的信号之和的一半电导率数据单元。非易失性存储器还包括偏置电压发生器，该偏置电压发生器使用高电导率非易失性参考单元作为参考，并且其产生偏置电压，该偏置电压耦合到读出放大器的输入处的限流晶体管，使得电流进入读出放大器是有限的，因此限制了非易失性存储器使用的功率。

3. 发明授权

US08093951B1 Pulse-width modulated (PWM) audio power amplifier having output signal magnitude controlled pulse voltage and switching frequency 有权
标题翻译：脉冲宽度调制（PWM）音频功率放大器具有输出信号幅值受控的脉冲电压和开关频率
公开(公告)号：US08093951B1
公开(公告)日：2012-01-10
申请号：US12568667
申请日：2009-09-28
申请人： Lingli Zhang , Dan Shen , Johann Gaboriau , Eric J. Swanson
发明人： Lingli Zhang , Dan Shen , Johann Gaboriau , Eric J. Swanson
IPC分类号： H03F3/217 , H03F3/04
CPC分类号： H03F3/217 , H03F2200/03 , H03F2200/114 , H03F2200/351
摘要： An audio switching power amplifier having an output pulse voltage selected in conformity with an indication of the output signal amplitude provides lower electromagnetic interference (EMI) in class-D amplifier implementations, in particular, in inductor-less designs. The output pulse voltage may be selected by providing multiple switching circuits, such as half or fully bridge switches, with each switching circuit connected to a different power supply. One of the switching circuits is activated by the switching controller, while the others are disabled, providing selection of the output pulse voltage. Selection of a lower pulse voltage, when the maximum voltage is not required, reduces the generated EMI. The switching frequency of the class-D amplifier may also be controlled in conformity with the output signal amplitude, so that at higher output levels a lower switching rate is selected, reducing the generated EMI.
摘要翻译：具有根据输出信号幅度的指示选择的输出脉冲电压的音频开关功率放大器在D类放大器实现中尤其是在无电感设计中提供较低的电磁干扰（EMI）。可以通过提供多个开关电路（例如半桥或全桥开关）来选择输出脉冲电压，每个开关电路连接到不同的电源。其中一个开关电路由开关控制器激活，而其他开关电路被禁用，提供输出脉冲电压的选择。当不需要最大电压时，选择较低的脉冲电压可以减少产生的EMI。 D类放大器的开关频率也可以根据输出信号幅度进行控制，从而在较高的输出电平下选择较低的开关速率，从而减少产生的EMI。

4. 发明授权

US06901423B1 Noise invariant circuits, systems and methods 有权
公开(公告)号：US06901423B1
公开(公告)日：2005-05-31
申请号：US09840530
申请日：2001-04-23
申请人： Edwin De Angel , Eric J. Swanson
发明人： Edwin De Angel , Eric J. Swanson
IPC分类号： G06F1/26 , G06F7/52 , G06F7/533 , G06J1/00
CPC分类号： G06F7/5336 , G06F2207/3868
摘要： The electrical circuitry for a multiplier system includes a counter for determining proximity to sampling operation, and a switch to select between symmetrical noise invariant operation and a low-power mode of operation. A noise invariant circuit disables row skip operation in a multi-row multiplier, to enable analog sampling. Disabling of the row skip operation is accomplished at a time which is several digital cycles preceding the time of analog sampling. Power saving multiplier row skippage resumes after analog sampling is completed.

5. 发明授权

US06590517B1 Analog to digital conversion circuitry including backup conversion circuitry 失效
标题翻译：模数转换电路包括备用转换电路
公开(公告)号：US06590517B1
公开(公告)日：2003-07-08
申请号：US10061791
申请日：2002-02-01
申请人： Eric J. Swanson
发明人： Eric J. Swanson
IPC分类号： H03M112
CPC分类号： H03M1/187 , H03M1/185 , H03M1/208
摘要： An autoranging analog to digital conversion system is provided. The system may include a digitally programmable preamplifier for amplifying a difference between an analog input and an estimate of the analog input. The preamplifier may be coupled to an analog to digital converter for converting the preamplifier output to a digital signal. The system may also include digital domain predictor or estimation logic for determining an optimum gain and analog input estimate for a given analog input. Multiple signal input channels may be coupled to the analog to digital conversion system. The autoranging estimations may be performed on a sample by sample basis or a channel by channel basis. The conversion system may also include the use of a backup conversion path for use when the main conversion path overranges. The backup conversion path may utilize a dedicated backup converter. The backup conversion path may alternatively utilize the estimation converter to generate backup conversions or may utilize the main converter to generate backup conversions.
摘要翻译：提供了一种自动量程模数转换系统。该系统可以包括用于放大模拟输入和模拟输入的估计之间的差的数字可编程前置放大器。前置放大器可以耦合到模数转换器，用于将前置放大器输出转换成数字信号。该系统还可以包括用于确定给定模拟输入的最佳增益和模拟输入估计的数字域预测器或估计逻辑。多个信号输入通道可以耦合到模数转换系统。自动量程估计可以根据样本或逐个频道进行。转换系统还可以包括使用备用转换路径，以便在主转换路径超出时使用。备用转换路径可以利用专用备用转换器。备选转换路径可以替代地使用估计转换器来产生备份转换，或者可以利用主转换器来生成备份转换。

6. 发明授权

US06356872B1 Method and apparatus for storing digital audio and playback thereof 失效
标题翻译：用于存储数字音频及其回放的方法和装置
公开(公告)号：US06356872B1
公开(公告)日：2002-03-12
申请号：US08719986
申请日：1996-09-25
申请人： Ka Yin Leung , Eric J. Swanson , Kafai Leung
发明人： Ka Yin Leung , Eric J. Swanson , Kafai Leung
IPC分类号： G10L2100
CPC分类号： G10L21/0364
摘要： A data conversion device is provided for storing digital data in a DAT (332) at a 16-bit word length and then recovering the data at a 24-bit word length with an overall reduction in truncation noise that would be inherently associated with data at the 16-bit word length. This is facilitated by noise shaping the data at the 16-bit word length prior to storage in the DAT (332) with a noise-shaping filter (324). This results in truncation noise in the lower portion of the frequency band being shifted to the higher portion of the band. When the data is recovered, it is converted to a 24-bit word length and then processed through a bandpass filter to filter out the higher frequency noise to yield a signal that has a maximum noise equal to or less than that in the lower portion of the band stored in the DAT (332). Since the truncation noise was shifted from the lower band to the upper band, this is a lower noise level than that inherently associated with the 16-bit word length.
摘要翻译：提供了一种数据转换装置，用于以16位字长将数字数据存储在DAT（332）中，然后以24位字长恢复数据，同时全局减少截断噪声，该截断噪声本质上与 16位字长。这通过在使用噪声整形滤波器（324）存储在DAT（332）中之前对16位字长的数据进行噪声整形来促进。这导致频带下部的截断噪声转移到频带的较高部分。当数据被恢复时，将其转换为24位字长，然后通过带通滤波器进行处理，以滤除更高频率的噪声，以产生最大噪声等于或小于存储在DAT（332）中的乐队。由于截断噪声从较低频带偏移到较高频带，因此与16位字长固有相关的噪声水平较低。

7. 发明授权

US06331785B1 Polling to determine optimal impedance 有权
标题翻译：轮询以确定最佳阻抗
公开(公告)号：US06331785B1
公开(公告)日：2001-12-18
申请号：US09641479
申请日：2000-08-18
申请人： Eric J. Swanson , Diwakar Vishakhadatta
发明人： Eric J. Swanson , Diwakar Vishakhadatta
IPC分类号： H03K1714
CPC分类号： H03H11/28 , H03F3/3023
摘要： A system and method is provided for providing optimal input and output impedances at a telecommunications interface. Input and output impedances can be adjusted manually, or the optimal impedance can be sensed and provided for automatically at the selected interface.
摘要翻译：提供了一种用于在电信接口处提供最佳输入和输出阻抗的系统和方法。可以手动调整输入和输出阻抗，或者可以在所选界面自动检测和提供最佳阻抗。

8. 发明授权

US5719573A Analog modulator for A/D converter utilizing leap-frog filter 失效
标题翻译：用于A / D转换器的模拟调制器利用跳跃式滤波器
公开(公告)号：US5719573A
公开(公告)日：1998-02-17
申请号：US457870
申请日：1995-06-01
申请人： Ka Yin Leung , Eric J. Swanson
发明人： Ka Yin Leung , Eric J. Swanson
IPC分类号： H03H19/00 , H03M3/02 , H03M3/00
CPC分类号： H03M3/448 , H03H19/004 , H03M3/43 , H03M3/452
摘要： An analog modulator is provided having seven switched-capacitor integrators (62)-(74) disposed in a leap-frog filter configuration with a plurality of feedback taps (76)-(88) provided from the output to each of the integrators (62)-(74). These are summed in a summation junction (90), the output thereof input to a quantizing circuit (92) for input back to a summation junction alter a D to A circuit (60) for summation with the analog input signal and then input to the first integrator (62). The first feedback structures (98)-(102) are provided for connection between the output of the last of the integrated structures (74) and the input of the preceding one thereof such that the feedback structure (98) is connected across integrators (64) and integrator (66), feedback structure (100) connected between integrators (68)-(70) and integrator (102) connected against integrators (72) and (74). Leap-frog feedback elements are connected across integrators (70) and (72) and leap-frog feedback filter (104) is connected across integrator (66) and (68).
摘要翻译：提供了一种模拟调制器，具有七个开关电容积分器（62） - （74），其布置在跨越滤波器配置中，具有从输出到每个积分器（62）提供的多个反馈抽头（76） - （88）） - （74）。这些在加法结（90）中相加，其输出被输入到量化电路（92），用于输入到加法结，改变D到A电路（60）以与模拟输入信号相加，然后输入到第一积分器（62）。第一反馈结构（98） - （102）被提供用于在最后一个集成结构（74）的输出和其前一个的输入之间连接，使得反馈结构（98）跨越积分器（64 ）和积分器（66），连接在与积分器（72）和（74）连接的积分器（68） - （70）和积分器（102）之间的反馈结构（100）。跨越反馈元件跨越积分器（70）和（72）连接，并且跨越积分器（66）和（68）的跨越式反馈滤波器（104）连接。

9. 发明授权

US4542304A Switched capacitor feedback sample-and-hold circuit 失效
标题翻译：开关电容器反馈采样保持电路
公开(公告)号：US4542304A
公开(公告)日：1985-09-17
申请号：US451026
申请日：1982-12-20
申请人： Eric J. Swanson
发明人： Eric J. Swanson
IPC分类号： G11C27/02
CPC分类号： G11C27/026
摘要： The feedback sample-and-hold stages of a transversal filter bank include a primary sample-and-hold branch and a secondary sample-and-hold branch for correction of offset voltage in the primary branch which results from switching charge feedthrough of its sampling switch. A pair of N-channel buffer transistors, one an enhancement type and one a depletion type, are so connected to the branches that power supply noise is attenuated. Additionally, the parasitic capacitance of the enhancement transistor acts as a coupling capacitor for the correction function.
摘要翻译：横向滤波器组的反馈采样和保持级包括初级采样保持分支和用于校正主分支中的偏移电压的次级采样保持分支，其由其采样开关的开关充电馈通产生。一对N沟道缓冲晶体管，一种增强型和一种耗尽型，被连接到电源噪声衰减的分支。此外，增强晶体管的寄生电容用作用于校正功能的耦合电容器。

10. 发明授权

US08008975B1 Gate-boosted, variable voltage supply rail amplifier 有权
标题翻译：门极升压，可变电源电源轨放大器
公开(公告)号：US08008975B1
公开(公告)日：2011-08-30
申请号：US12415788
申请日：2009-03-31
申请人： Daniel J. Allen , Eric J. Swanson , Scott A. Woodford
发明人： Daniel J. Allen , Eric J. Swanson , Scott A. Woodford
IPC分类号： H03F3/04
CPC分类号： H03F3/3022 , H03F1/0216 , H03F3/45475 , H03F2200/513
摘要： In at least one embodiment, an electronic system includes an amplifier having an on-chip charge pump to provide a gate boost voltage to boost a gate voltage of at least one on-chip field effect transistor (FET) of an output stage of an amplifier. In at least one embodiment, the gate boost voltage boosts the gate voltage higher than the supply voltage rail to increase an overdrive voltage of the on-chip FET. In at least one embodiment, the gate boost voltage boosts the DC bias of an input signal and, thus, generation of gate boost voltage by the on-chip charge pump is signal-independent, i.e. independent of the input signal. Increasing the overdrive voltage increases the efficiency of the amplifier by decreasing the difference between the maximum swing of the output voltage and the voltage supply rails of the at least one on-chip FET relative to conventional designs.
摘要翻译：在至少一个实施例中，电子系统包括具有片上电荷泵的放大器，以提供栅极升压电压以升高放大器的输出级的至少一个片上场效应晶体管（FET）的栅极电压。在至少一个实施例中，栅极升压电压将栅极电压升高高于电源电压轨，以增加片上FET的过驱动电压。在至少一个实施例中，栅极升压电压升高输入信号的DC偏置，因此片上电荷泵的栅极升压电压的产生与信号无关，即独立于输入信号。通过减小输出电压的最大摆动和至少一个片上FET的电压供应轨之间的差异，相对于常规设计，增加过驱动电压增加了放大器的效率。

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