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1. 发明授权

US10968619B2 Architectural construction technique 有权
公开(公告)号：US10968619B2
公开(公告)日：2021-04-06
申请号：US16509899
申请日：2019-07-12
申请人： David L. Harmon
发明人： David L. Harmon
IPC分类号： E04B1/30 , E04B1/14 , E04B1/84 , E04B1/94 , E04F15/02 , E04B5/48 , E04B1/66 , E04B1/88 , E04F15/10
摘要： A construction technique, for example for residential, light commercial and multifamily building construction, involving pre-fabricated elements. The elements include prefabricated structural components and prefabricated surface components. A technique of incremental building includes assembling a building structure using these pre-fabricated elements.

2. 发明授权

US5204138A Plasma enhanced CVD process for fluorinated silicon nitride films 失效
标题翻译：氟化氮化硅膜的等离子体增强CVD工艺
公开(公告)号：US5204138A
公开(公告)日：1993-04-20
申请号：US814973
申请日：1991-12-24
申请人： Son V. Nguyen , David M. Dobuzinsky , Douglas J. Dopp , David L. Harmon
发明人： Son V. Nguyen , David M. Dobuzinsky , Douglas J. Dopp , David L. Harmon
IPC分类号： C23C14/06 , C23C16/34 , C23C16/505 , C30B25/02 , H01L21/318
CPC分类号： C23C16/505 , C23C16/345
摘要： A plasma enhanced chemical vapor deposition process for producing a fluorinated silicon nitride layer on a substrate is disclosed. The process utilizes a mixture of silane, perfluorosilane and nitrogen to produce films of high conformality and stability. The silane and perfluorosilane in the mixture are in a ratio of 0.05 to 1 on a volume basis. The preferred silane is SiH.sub.4 and the preferred perfluorosilane is SiF.sub.4.
摘要翻译：公开了一种用于在衬底上制造氟化氮化硅层的等离子体增强化学气相沉积工艺。该方法利用硅烷，全氟硅烷和氮气的混合物来制备具有高共形性和稳定性的膜。混合物中的硅烷和全氟硅烷的体积比为0.05-1。优选的硅烷是SiH 4，优选的全氟硅烷是SiF 4。

3. 发明申请

US20200018057A1 Architectural Construction Technique 审中-公开
公开(公告)号：US20200018057A1
公开(公告)日：2020-01-16
申请号：US16509899
申请日：2019-07-12
申请人： David L. Harmon
发明人： David L. Harmon
IPC分类号： E04B1/14 , E04B1/30 , E04B1/84 , E04B1/94 , E04F15/02 , E04F15/10 , E04B5/48 , E04B1/66 , E04B1/88
摘要： A construction technique, for example for residential, light commercial and multifamily building construction, involving pre-fabricated elements. The elements include prefabricated structural components and prefabricated surface components. A technique of incremental building includes assembling a building structure using these pre-fabricated elements.

4. 发明授权

US07132318B2 Method of assessing potential for charging damage in SOI designs and structures for eliminating potential for damage 有权
标题翻译：评估SOI设计和结构中充电损害潜力的方法，以消除损坏的可能性
公开(公告)号：US07132318B2
公开(公告)日：2006-11-07
申请号：US11003988
申请日：2004-12-04
申请人： Henry A. Bonges, III , David L. Harmon , Terence B. Hook , Wing L. Lai
发明人： Henry A. Bonges, III , David L. Harmon , Terence B. Hook , Wing L. Lai
IPC分类号： H01L21/00 , H01L21/336 , H01L21/8234
CPC分类号： H01L27/0251
摘要： Disclosed is a method and structure for altering an integrated circuit design having silicon over insulator (SOI) transistors. The method/structure prevents damage from charging during processing to the gate of SOI transistors by tracing electrical nets in the integrated circuit design, identifying SOI transistors that may have a voltage differential between the source/drain and gate as potentially damaged SOI transistors (based on the tracing of the electrical nets), and connecting a shunt device across the source/drain and the gate of each of the potentially damaged SOI transistors. Alternatively, the method/structure provides for connecting compensating conductors through a series device.
摘要翻译：公开了一种用于改变具有绝缘体上硅（SOI）晶体管的集成电路设计的方法和结构。该方法/结构通过在集成电路设计中跟踪电网来防止在处理到SOI晶体管的栅极期间的充电损坏，识别可能在源极/漏极和栅极之间具有电压差的SOI晶体管作为潜在损坏的SOI晶体管（基于电网的跟踪），以及在每个潜在损坏的SOI晶体管的源极/漏极和栅极之间连接分流器件。或者，方法/结构提供通过串联装置连接补偿导体。

5. 发明授权

US5412246A Low temperature plasma oxidation process 失效
标题翻译：低温等离子体氧化工艺
公开(公告)号：US5412246A
公开(公告)日：1995-05-02
申请号：US186568
申请日：1994-01-26
申请人： David M. Dobuzinsky , David L. Harmon , Srinandan R. Kasi , Donald M. Kenney , Son V. Nguyen , Tue Nguyen , Pai-Hung Pan
发明人： David M. Dobuzinsky , David L. Harmon , Srinandan R. Kasi , Donald M. Kenney , Son V. Nguyen , Tue Nguyen , Pai-Hung Pan
IPC分类号： C23C8/36 , H01L21/31 , H01L21/316 , H01L21/321 , H01L21/8242 , H01L27/108 , H01L29/12
CPC分类号： H01L21/32105 , H01L21/02238 , H01L21/02252 , H01L21/31662 , Y10S148/118 , Y10S257/90
摘要： A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree. C., preferably about 350.degree.-400.degree. C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100 .ANG.. An oxide film of uniform thickness is formed by controlling the temperature, RF power, exposure time and oxygen/ozone ratio for thin gate oxide (
摘要翻译：一种在半导体器件的表面上形成薄膜的工艺。该方法包括通过等离子体增强的热氧化形成二氧化硅膜，采用臭氧和氧的混合物，其以反应器室分开产生，体积比约为1-10 / 1，优选约5-7 / 1，在一般低于440℃，优选约350-400℃的温度下进行。该方法用于在场效应晶体管的多晶硅栅上形成侧壁氧化物间隔物。在显着低于常规氧化工艺中使用的温度下实现相对较快的氧化速率，这用于减少掺杂剂从多晶硅的扩散。此外，所得膜表现出低应力，并具有多晶硅栅极的良好的共形台阶覆盖。该方法的另一个用途是生长厚度小于100安培的薄栅氧化物和氧化物 - 氮化物 - 氧化物。通过控制ULSI FET制造中薄栅氧化物（<100 ANGSTROM）应用的温度，RF功率，曝光时间和氧/臭氧比，形成均匀厚度的氧化膜。

6. 发明授权

US08492866B1 Isolated Zener diode 有权
标题翻译：隔离齐纳二极管
公开(公告)号：US08492866B1
公开(公告)日：2013-07-23
申请号：US13345881
申请日：2012-01-09
申请人： Frederick G. Anderson , Natalie B. Feilchenfeld , David L. Harmon , Richard A. Phelps , Yun Shi , Michael J. Zierak
发明人： Frederick G. Anderson , Natalie B. Feilchenfeld , David L. Harmon , Richard A. Phelps , Yun Shi , Michael J. Zierak
IPC分类号： H01L29/861 , H01L31/107 , H01L29/30 , H01L29/866 , H01L29/34 , H01L29/74 , H01L31/111 , H01L29/73 , H01L29/739 , H01L31/0328 , H01L31/0336 , H01L31/072 , H01L31/109 , H01L29/00 , H01L29/864
CPC分类号： H01L29/866 , H01L21/76 , H01L21/76283 , H01L27/0255 , H01L29/66106
摘要： Disclosed is a Zener diode having a scalable reverse-bias breakdown voltage (Vb) as a function of the position of a cathode contact region relative to the interface between adjacent cathode and anode well regions. Specifically, cathode and anode contact regions are positioned adjacent to corresponding cathode and anode well regions and are further separated by an isolation region. However, while the anode contact region is contained entirely within the anode well region, one end of the cathode contact region extends laterally into the anode well region. The length of this end can be predetermined in order to selectively adjust the Vb of the diode (e.g., increasing the length reduces Vb of the diode and vice versa). Also disclosed are an integrated circuit, incorporating multiple instances of the diode with different reverse-bias breakdown voltages, a method of forming the diode and a design structure for the diode.
摘要翻译：公开了一种齐纳二极管，其具有作为阴极接触区域相对于相邻阴极和阳极阱区域之间的界面的位置的函数的可分级反向偏压击穿电压（Vb）。具体地，阴极和阳极接触区域被定位成与相应的阴极和阳极阱区域相邻，并进一步被隔离区域分离。然而，当阳极接触区域完全包含在阳极阱区域内时，阴极接触区域的一端横向延伸到阳极阱区域中。为了选择性地调节二极管的Vb（例如，增加长度减小二极管的Vb，反之亦然），可以预定该端的长度。还公开了一种集成电路，其结合具有不同反向偏压击穿电压的二极管的多个实例，形成二极管的方法和二极管的设计结构。

7. 外观设计

USD674514S1 Radiant heat floor panel 有权
标题翻译：辐射热地板面板
公开(公告)号：USD674514S1
公开(公告)日：2013-01-15
申请号：US29373748
申请日：2011-05-18
申请人： David L. Harmon
设计人： David L. Harmon

8. 发明申请

US20120076172A1 MICRO-ELECTRO-MECHANICAL-SYSTEM TEMPERATURE SENSOR 失效
标题翻译：微电子机械系统温度传感器
公开(公告)号：US20120076172A1
公开(公告)日：2012-03-29
申请号：US12892406
申请日：2010-09-28
申请人： Jason P. Gill , David L. Harmon , Timothy D. Sullivan
发明人： Jason P. Gill , David L. Harmon , Timothy D. Sullivan
IPC分类号： G01K5/52
CPC分类号： G01K5/52
摘要： The present invention provides a micro-electro-mechanical-system (MEMS) temperature sensor that employs a suspended spiral comprising a material with a positive coefficient of thermal expansion. The thermal expansion of the suspended spiral is guided to by a set of guideposts to provide a linear movement of the free end of the suspended spiral, which is converted to an electrical signal by a set of conductive rotor azimuthal fins that are interdigitated with a set of conductive stator azimuthal fins by measuring the amount of capacitive coupling therebetween. Real time temperature may thus be measured through the in-situ measurement of the capacitive coupling. Optionally, the MEMS temperature sensor may have a ratchet and a pawl to enable ex-situ measurement.
摘要翻译：本发明提供了一种微电子机械系统（MEMS）温度传感器，其采用悬浮螺旋，其包括具有正的热膨胀系数的材料。悬挂螺旋的热膨胀由一组导轨引导以提供悬挂螺旋的自由端的线性运动，其被一组导电转子方位角翅片转换成电信号，所述导电转子方位角翅片与组相互指向通过测量导电定子方位翅片之间的电容耦合量。因此可以通过电容耦合的原位测量来测量实时温度。可选地，MEMS温度传感器可以具有棘轮和棘爪以使得能够进行非原位测量。

9. 发明授权

US5118384A Reactive ion etching buffer mask 失效
标题翻译：反应离子蚀刻缓冲掩模
公开(公告)号：US5118384A
公开(公告)日：1992-06-02
申请号：US807960
申请日：1991-12-10
申请人： David L. Harmon , Michael L. Kerbaugh , Nancy T. Pascoe , John F. Rembetski
发明人： David L. Harmon , Michael L. Kerbaugh , Nancy T. Pascoe , John F. Rembetski
IPC分类号： H01L21/3065 , H01L21/308
CPC分类号： H01L21/3065 , H01L21/3085
摘要： An improved mask and method of forming a deep and uniform width trench in a substrate and the resulting structure is disclosed. A substrate material such as silicon has deposited thereon a first layer of sacrificial material as a first component of an etch mask, the sacrificial material being a material such as polysilicon that is either etched by or absorbs the same ions which reactively ion etch the substrate. A second layer of material, which resists reactive ion etching, such as silicon dioxide, is deposited over the first layer of material as a second component of the etch mask. The silicon dioxide is patterned in the form of the trench to be formed in the substrate. The layer polysilicon material is then reactive ion etched and the reactive ion etching continued to form a trench in the silicon substrate. The polysilicon acts as a sacrificial material being etched by any ions that are reflected from the silicon dioxide or are directed at an angle such that they strike the layer of polysilicon material. Thus, only those ions which are directed essentially normal to the underlying substrate perform the trench etching. This allows the trench to have essentially straight side walls and to be of essentially uniform width.
摘要翻译：公开了一种在衬底中形成深而均匀的宽度沟槽的改进的掩模和方法，并且所得到的结构被公开。诸如硅的衬底材料在其上沉积有第一层牺牲材料作为蚀刻掩模的第一组分，牺牲材料是诸如多晶硅的材料，其被蚀刻或吸收相同的离子，其反应离子蚀刻衬底。作为蚀刻掩模的第二组分，第二层材料，其抵抗反应离子蚀刻，例如二氧化硅，沉积在第一材料层上。二氧化硅以形成在衬底中的沟槽的形式构图。然后层状多晶硅材料被反应离子蚀刻，并且反应离子蚀刻继续在硅衬底中形成沟槽。多晶硅充当被二氧化硅反射的任何离子蚀刻的牺牲材料，或以一定角度被引导使得它们撞击多晶硅材料层。因此，仅基本上垂直于下面的衬底的那些离子执行沟槽蚀刻。这允许沟槽具有基本上直的侧壁并且具有基本均匀的宽度。

10. 发明授权

US08480302B2 Micro-electro-mechanical-system temperature sensor 失效
标题翻译：微机电系统温度传感器
公开(公告)号：US08480302B2
公开(公告)日：2013-07-09
申请号：US12892406
申请日：2010-09-28
申请人： Jason P. Gill , David L. Harmon , Timothy D. Sullivan
发明人： Jason P. Gill , David L. Harmon , Timothy D. Sullivan
IPC分类号： G01K5/00 , G01K7/00
CPC分类号： G01K5/52
摘要： The present invention provides a micro-electro-mechanical-system (MEMS) temperature sensor that employs a suspended spiral comprising a material with a positive coefficient of thermal expansion. The thermal expansion of the suspended spiral is guided to by a set of guideposts to provide a linear movement of the free end of the suspended spiral, which is converted to an electrical signal by a set of conductive rotor azimuthal fins that are interdigitated with a set of conductive stator azimuthal fins by measuring the amount of capacitive coupling therebetween. Real time temperature may thus be measured through the in-situ measurement of the capacitive coupling. Optionally, the MEMS temperature sensor may have a ratchet and a pawl to enable ex-situ measurement.
摘要翻译：本发明提供了一种微电子机械系统（MEMS）温度传感器，其采用悬浮螺旋，其包括具有正的热膨胀系数的材料。悬挂螺旋的热膨胀由一组导轨引导以提供悬挂螺旋的自由端的线性运动，其被一组导电转子方位角翅片转换成电信号，所述导电转子方位角翅片与组相互指向通过测量导电定子方位翅片之间的电容耦合量。因此可以通过电容耦合的原位测量来测量实时温度。可选地，MEMS温度传感器可以具有棘轮和棘爪以使得能够进行非原位测量。

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