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1. 发明授权

US6060393A Deposition control of stop layer and dielectric layer for use in the formation of local interconnects 失效
标题翻译：用于形成局部互连的停止层和介电层的沉积控制
公开(公告)号：US6060393A
公开(公告)日：2000-05-09
申请号：US993888
申请日：1997-12-18
申请人： Minh Van Ngo , Darin A. Chan , David K. Foote
发明人： Minh Van Ngo , Darin A. Chan , David K. Foote
IPC分类号： H01L21/768 , H01L21/304
CPC分类号： H01L21/76895 , H01L21/76801
摘要： A deposition method allows for the forming of a uniform dielectric stop layer that is substantially void of defects caused by outgassing effects. The stop layer is deposited in a reactor chamber at a higher than normal temperature of at least 480.degree. C. The stop layer is then combined with an overlying dielectric layer to provide an inter-level dielectric structure through which a local interconnect can be formed to provide a conductive path to one or more regions of the underlying semiconductor devices.
摘要翻译：沉积方法允许形成基本上没有由除气效应引起的缺陷的均匀的电介质停止层。停止层沉积在高于至少480℃的常温的反应器室中。然后将停止层与覆盖的介电层组合以提供层间电介质结构，通过该层间电介质结构可以形成局部互连为下面的半导体器件的一个或多个区域提供导电路径。

2. 发明授权

US06903007B1 Process for forming bottom anti-reflection coating for semiconductor fabrication photolithography which inhibits photoresist footing 失效
标题翻译：用于形成抑制光致抗蚀剂底物的用于半导体制造光刻的底部抗反射涂层的方法
公开(公告)号：US06903007B1
公开(公告)日：2005-06-07
申请号：US08857055
申请日：1997-05-15
申请人： David K. Foote , Minh Van Ngo
发明人： David K. Foote , Minh Van Ngo
IPC分类号： H01L21/027 , H01L21/312 , H01L21/314 , H01L21/768 , H01L23/522 , H01L21/4763
CPC分类号： H01L21/02126 , H01L21/02274 , H01L21/0234 , H01L21/02362 , H01L21/0276 , H01L21/3121 , H01L21/3144 , H01L21/3145 , H01L21/76802 , H01L21/76895 , H01L23/5226 , H01L2924/0002 , H01L2924/00
摘要： An anti-reflective coating is formed between a material layer which is to be patterned on a semiconductor structure using photolithography, and an overlying photoresist layer. The anti-reflective coating suppresses reflections from the material layer surface into the photoresist layer that could degrade the patterning. The anti-reflective coating includes an anti-reflective layer of silicon oxime, silicon oxynitride, or silicon nitride, and a barrier layer which is grown on the anti-reflective layer using a nitrous oxide plasma discharge to convert a surface portion of the anti-reflective layer into silicon dioxide. The barrier layer prevents interaction between the anti-reflective layer and the photoresist layer that could create footing. The anti-reflective layer is deposited on the material layer using Plasma Enhanced Chemical Vapor Deposition (PECVD) in a reactor. The barrier layer is grown on the anti-reflective layer in-situ in the same reactor, thereby maximizing throughput.
摘要翻译：在使用光刻法在半导体结构上图案化的材料层和上覆的光致抗蚀剂层之间形成抗反射涂层。抗反射涂层抑制从材料层表面到可能降解图案化的光致抗蚀剂层的反射。抗反射涂层包括硅肟，氮氧化硅或氮化硅的抗反射层，以及阻挡层，其使用一氧化二氮等离子体放电在抗反射层上生长以将抗反射层转化成抗反射层，反射层成二氧化硅。阻挡层防止可产生基底的抗反射层和光致抗蚀剂层之间的相互作用。在反应器中使用等离子体增强化学气相沉积（PECVD）将抗反射层沉积在材料层上。阻挡层在同一反应器中原位生长在抗反射层上，从而最大化生产量。

3. 发明授权

US06380588B1 Semiconductor device having uniform spacers 有权
标题翻译：具有均匀间隔物的半导体器件
公开(公告)号：US06380588B1
公开(公告)日：2002-04-30
申请号：US09567013
申请日：2000-05-09
申请人： William G. En , Minh Van Ngo , Chih-Yuk Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuk Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L2100
CPC分类号： H01L21/31116
摘要： A semiconductor device having both functional and non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.
摘要翻译：具有功能和非功能或虚拟线，区域和/或图案的半导体器件，以产生导致随后形成的间隔物在形状和尺寸上更可预测和均匀的拓扑。

4. 发明授权

US6103611A Methods and arrangements for improved spacer formation within a semiconductor device 失效
标题翻译：用于改善半导体器件内的间隔物形成的方法和布置
公开(公告)号：US6103611A
公开(公告)日：2000-08-15
申请号：US993830
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L21/311 , H01L21/00 , H01L21/3065
CPC分类号： H01L21/31116
摘要： Methods and arrangements are provided to increase the process control during the formation of spacers within a semiconductor device. The methods and arrangements include the use of non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.
摘要翻译：提供了在半导体器件内形成间隔物期间增加工艺控制的方法和装置。这些方法和布置包括使用非功能或虚拟线，区域和/或图案来创建导致随后形成的间隔物在形状和尺寸上更可预测和均匀的拓扑。

5. 发明授权

US06399480B1 Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction 有权
标题翻译：用于绝缘局部互连的方法和布置，以改善对准公差和减小尺寸
公开(公告)号：US06399480B1
公开(公告)日：2002-06-04
申请号：US09515319
申请日：2000-02-29
申请人： William G. En , Darin A. Chan , David K. Foote , Fei Wang , Minh Van Ngo
发明人： William G. En , Darin A. Chan , David K. Foote , Fei Wang , Minh Van Ngo
IPC分类号： H01L714263
CPC分类号： H01L21/76895 , H01L21/76897
摘要： At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting,the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.
摘要翻译：在晶体管布置内提供至少一个图案化的介电层，以防止局部互连在形成局部互连的蚀刻开口的镶嵌层形成期间由于不对准导致栅极导体电接触。通过在局部互连蚀刻工艺期间通过选择性蚀刻穿过多个电介质层，将图案化的介电层留在原位以防止栅极短路到相邻的局部互连，其稍微错位。

6. 发明授权

US06395644B1 Process for fabricating a semiconductor device using a silicon-rich silicon nitride ARC 有权
标题翻译：使用富硅氮化物ARC制造半导体器件的工艺
公开(公告)号：US06395644B1
公开(公告)日：2002-05-28
申请号：US09484606
申请日：2000-01-18
申请人： Dawn M. Hopper , Minh Van Ngo , David K. Foote
发明人： Dawn M. Hopper , Minh Van Ngo , David K. Foote
IPC分类号： H01L21302
CPC分类号： H01L21/3185 , H01L21/32139 , Y10S438/952
摘要： A process for fabricating a semiconductor device using an ARC layer includes the formation of a silicon-rich silicon nitride material to provide an anti-reflective layer over a electrically conductive or semiconductor surface. The silicon-rich silicon nitride material is plasma deposited to provide a material having a desired refractive index, thickness uniformity, and density. The process includes the formation of a device layer on a semiconductor substrate. The device layer includes at least a silicon layer and a silicon oxide layer. A silicon-rich silicon nitride layer is formed to overlie the device layer. The silicon-rich silicon nitride material can be selectively etched, such that the silicon material and the silicon oxide material in the underlying device layer are not substantially etched.
摘要翻译：使用ARC层制造半导体器件的方法包括形成富硅的氮化硅材料，以在导电或半导体表面上提供抗反射层。富硅氮化硅材料被等离子体沉积以提供具有期望的折射率，厚度均匀性和密度的材料。该方法包括在半导体衬底上形成器件层。器件层至少包括硅层和氧化硅层。形成富含硅的氮化硅层以覆盖器件层。可以选择性地蚀刻富硅的氮化硅材料，使得底层器件层中的硅材料和氧化硅材料基本上不被蚀刻。

7. 发明授权

US6121663A Local interconnects for improved alignment tolerance and size reduction 失效
标题翻译：局部互连，用于改善对准公差和减小尺寸
公开(公告)号：US6121663A
公开(公告)日：2000-09-19
申请号：US992952
申请日：1997-12-18
申请人： William G. En , Darin A. Chan , David K. Foote , Fei Wang , Minh Van Ngo
发明人： William G. En , Darin A. Chan , David K. Foote , Fei Wang , Minh Van Ngo
IPC分类号： H01L21/60 , H01L21/768 , H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113
CPC分类号： H01L21/76895 , H01L21/76897
摘要： At least one patterned dielectric layer is provided within a transistor arrangement to prevent a local interconnect from electrically contacting the gate conductor due to misalignments during the damascene formation of etched openings used in forming local interconnects. By selectively etching through a plurality of dielectric layers during the local interconnect etching process, the patterned dielectric layer is left in place to prevent short-circuiting of the gate to an adjacent local interconnect that is slightly misaligned.
摘要翻译：在晶体管布置内提供至少一个图形化的介电层，以防止局部互连在形成局部互连所用的蚀刻开口的镶嵌层形成期间由于不对准而电接触栅极导体。通过在局部互连蚀刻工艺期间通过选择性蚀刻穿过多个电介质层，将图案化的介电层留在原位以防止栅极短路到相邻的局部互连，其稍微错位。

8. 发明授权

US5990524A Silicon oxime spacer for preventing over-etching during local interconnect formation 失效
标题翻译：硅肟间隔物，用于在局部互连形成期间防止过蚀刻
公开(公告)号：US5990524A
公开(公告)日：1999-11-23
申请号：US993868
申请日：1997-12-18
申请人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
发明人： William G. En , Minh Van Ngo , Chih-Yuh Yang , David K. Foote , Scott A. Bell , Olov B. Karlsson , Christopher F. Lyons
IPC分类号： H01L21/768 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/76895
摘要： During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. Improved, multipurpose spacers are provided to reduce the chances of over-etching. The multipurpose spacers are made of silicon oxime. The etching plasmas that are used to etch one or more overlying dielectric layers tend to have a higher selectivity ratio to the multipurpose spacers than to the conventional oxide spacers. Additionally, the multipurpose spacers do not tend to degrade the hot carrier injection (HCI) properties as would a typical nitride spacer.
摘要翻译：在半导体晶片中局部互连的镶嵌形成期间，由于将与晶体管栅极相邻的氧化物间隔物暴露于用于蚀刻一个或多个蚀刻等离子体的一个或多个蚀刻等离子体，可以将穿透区域形成为衬底，更重叠的电介质层。穿通区域可能会损坏晶体管电路。提供改进的多用途间隔件以减少过度蚀刻的机会。多用途间隔件由硅肟制成。用于蚀刻一个或多个上覆电介质层的蚀刻等离子体与常规氧化物间隔物相比往往具有比多用途间隔物更高的选择比。此外，多用途间隔物不会像典型的氮化物间隔物一样降低热载流子注入（HCl）性质。

9. 发明授权

US5963841A Gate pattern formation using a bottom anti-reflective coating 失效
标题翻译：使用底部抗反射涂层的栅格图案形成
公开(公告)号：US5963841A
公开(公告)日：1999-10-05
申请号：US924370
申请日：1997-09-05
申请人： Olov B. Karlsson , Christopher F. Lyons , Minh Van Ngo , Scott A. Bell , David K. Foote
发明人： Olov B. Karlsson , Christopher F. Lyons , Minh Van Ngo , Scott A. Bell , David K. Foote
IPC分类号： H01L21/3213 , H01L21/302
CPC分类号： H01L21/32139
摘要： A gate is formed on a semiconductor substrate by using a bottom anti-reflective coating (BARC) to better control the critical dimension (CD) of the gate as defined via a deep-UV resist mask formed thereon. The wafer stack includes a gate oxide layer over a semiconductor substrate, a polysilicon gate layer over the gate oxide layer, a SiON BARC over the conductive layer, a thin oxide film over the SiON BARC. The resist mask is formed on the oxide film. The SiON BARC improves the resist mask formation process. The wafer stack is then shaped to form one or more polysilicon gates by sequentially etching through selected portions of the oxide film, the BARC, and the gate conductive layer as defined by the etch windows in the resist mask. Once properly shaped, the remaining portions of the resist mask, oxide film and SiON BARC are removed.
摘要翻译：通过使用底部抗反射涂层（BARC）在半导体衬底上形成栅极以更好地控制通过形成在其上的深UV抗蚀剂掩模所限定的栅极的临界尺寸（CD）。晶片堆叠包括半导体衬底上的栅极氧化物层，栅极氧化物层上的多晶硅栅极层，导电层上的SiON BARC，SiON BARC上的薄氧化物膜。在氧化物膜上形成抗蚀剂掩模。 SiON BARC改进了抗蚀剂掩模形成过程。然后通过依次蚀刻通过抗蚀剂掩模中由蚀刻窗口限定的氧化膜，BARC和栅极导电层的选定部分，将晶片堆叠成形以形成一个或多个多晶硅栅极。一旦适当成形，就去除了抗蚀剂掩模，氧化膜和SiON BARC的其余部分。

10. 发明授权

US5895269A Methods for preventing deleterious punch-through during local interconnect formation 失效
标题翻译：在局部互连形成期间防止有害穿透的方法
公开(公告)号：US5895269A
公开(公告)日：1999-04-20
申请号：US993887
申请日：1997-12-18
申请人： Fei Wang , Minh Van Ngo , Darin A. Chan , David K. Foote , William G. En
发明人： Fei Wang , Minh Van Ngo , Darin A. Chan , David K. Foote , William G. En
IPC分类号： H01L21/336 , H01L21/768 , H01L21/28 , H01L21/3205
CPC分类号： H01L29/6659 , H01L21/76895
摘要： During damascene formation of local interconnects in a semiconductor wafer, a punch-through region can be formed into the substrate as a result of exposing the oxide spacers that are adjacent to a transistor gate to one or more etching plasmas that are used to etch one or more overlying dielectric layers. A punch-through region can damage the transistor circuit. In order to prevent punch-through, the oxide spacers are removed prior to forming an overlying dielectric layer.
摘要翻译：在半导体晶片中局部互连的镶嵌形成期间，由于将与晶体管栅极相邻的氧化物间隔物暴露于用于蚀刻一个或多个蚀刻等离子体的一个或多个蚀刻等离子体，可以将穿透区域形成为衬底，更重叠的电介质层。穿通区域可能会损坏晶体管电路。为了防止穿透，在形成覆盖的介电层之前去除氧化物间隔物。

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