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1. 发明授权

US06924185B2 Fuse structure and method to form the same 失效
标题翻译：保险丝结构和方法形成相同
公开(公告)号：US06924185B2
公开(公告)日：2005-08-02
申请号：US10680618
申请日：2003-10-07
申请人： David K. Anderson , Tien-Jen Cheng , Timothy J. Dalton , Christopher V. Jahnes , Andrew Lu , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant , George F. Walker
发明人： David K. Anderson , Tien-Jen Cheng , Timothy J. Dalton , Christopher V. Jahnes , Andrew Lu , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant , George F. Walker
IPC分类号： H01L23/525 , H01L21/336
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.
摘要翻译：用于熔丝结构的方法和结构包括绝缘体层，穿过绝缘体层延伸到下面的布线层的多个熔丝电极，连接到电极的电镀熔丝元件和界面壁。保险丝元件位于绝缘体的外部，并且在绝缘体和保险丝元件之间并置有间隙。界面壁还包括第一侧壁，第二侧壁和内壁，其中内壁设置在间隙内。熔丝电极彼此直径相对，并且熔丝元件垂直地设置在熔丝电极的上方。保险丝元件是电镀，无电镀，或是超薄保险丝。

2. 发明授权

US06927472B2 Fuse structure and method to form the same 失效
公开(公告)号：US06927472B2
公开(公告)日：2005-08-09
申请号：US09992344
申请日：2001-11-14
申请人： David K. Anderson , Tien-Jen Cheng , Timothy J. Dalton , Christopher V. Jahnes , Andrew Lu , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant , George F. Walker
发明人： David K. Anderson , Tien-Jen Cheng , Timothy J. Dalton , Christopher V. Jahnes , Andrew Lu , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant , George F. Walker
IPC分类号： H01L23/525 , H01L21/336
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method and structure for a fuse structure comprises an insulator layer, a plurality of fuse electrodes extending through the insulator layer to an underlying wiring layer, an electroplated fuse element connected to the electrodes, and an interface wall. The fuse element is positioned external to the insulator, with a gap juxtaposed between the insulator and the fuse element. The interface wall further comprises a first side wall, a second side wall, and an inner wall, wherein the inner wall is disposed within the gap. The fuse electrodes are diametrically opposed to one another, and the fuse element is perpendicularly disposed above the fuse electrodes. The fuse element is either electroplatted, electroless plated, or is an ultra thin fuse.

3. 发明授权

US06831363B2 Structure and method for reducing thermo-mechanical stress in stacked vias 有权
标题翻译：用于降低堆叠过孔中热机械应力的结构和方法
公开(公告)号：US06831363B2
公开(公告)日：2004-12-14
申请号：US10319032
申请日：2002-12-12
申请人： Timothy J. Dalton , Sanjit K. Das , Brett H. Engel , Brian W. Herbst , Habib Hichri , Bernd E. Kastenmeier , Kelly Malone , Jeffrey R. Marino , Arthur Martin , Vincent J. McGahay , Ian D. Melville , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant
发明人： Timothy J. Dalton , Sanjit K. Das , Brett H. Engel , Brian W. Herbst , Habib Hichri , Bernd E. Kastenmeier , Kelly Malone , Jeffrey R. Marino , Arthur Martin , Vincent J. McGahay , Ian D. Melville , Chandrasekhar Narayan , Kevin S. Petrarca , Richard P. Volant
IPC分类号： H01L2348
CPC分类号： H01L21/76808 , H01L21/76801 , H01L21/76831 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.
摘要翻译：用于半导体器件的互连结构包括在较低金属化水平上形成的有机低介电常数（低k）电介质层。形成的通孔在低k电介质层内，通孔连接在下金属化层形成的下金属化线与上金属化层形成的上金属化线。通孔被选自具有热膨胀系数（CTE）的材料的结构轴环包围，以便在低k电介质层的热膨胀之后保护通孔不受剪切力的影响。

4. 发明授权

US06534863B2 Common ball-limiting metallurgy for I/O sites 有权
公开(公告)号：US06534863B2
公开(公告)日：2003-03-18
申请号：US09781121
申请日：2001-02-09
申请人： George F. Walker , Ronald D. Goldblatt , Peter A. Gruber , Raymond R. Horton , Kevin S. Petrarca , Richard P. Volant , Tien-Jen Cheng
发明人： George F. Walker , Ronald D. Goldblatt , Peter A. Gruber , Raymond R. Horton , Kevin S. Petrarca , Richard P. Volant , Tien-Jen Cheng
IPC分类号： H01L2348
CPC分类号： H01L24/48 , H01L21/76865 , H01L21/76873 , H01L21/76879 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/13 , H01L24/45 , H01L24/85 , H01L2224/0401 , H01L2224/04042 , H01L2224/04073 , H01L2224/05083 , H01L2224/05139 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05169 , H01L2224/05181 , H01L2224/05556 , H01L2224/05572 , H01L2224/05644 , H01L2224/05664 , H01L2224/05669 , H01L2224/11912 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2224/13116 , H01L2224/16 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/48644 , H01L2224/48664 , H01L2224/48669 , H01L2224/85201 , H01L2224/85203 , H01L2224/85205 , H01L2224/85207 , H01L2924/0001 , H01L2924/0002 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01024 , H01L2924/01028 , H01L2924/01029 , H01L2924/01042 , H01L2924/01047 , H01L2924/0105 , H01L2924/01072 , H01L2924/01073 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/014 , H01L2924/04953 , H01L2924/05042 , H01L2924/14 , H01L2924/30105 , H01L2924/00014 , H01L2924/00 , H01L2224/05552 , H01L2924/00015 , H01L2924/00012
摘要： A process is described for forming a common input-output (I/O) site that is suitable for both wire-bond and solder bump flip chip connections, such as controlled-collapse chip connections (C4). The present invention is particularly suited to semiconductor chips that use copper as the interconnection material, in which the soft dielectrics used in manufacturing such chips are susceptible to damage due to bonding forces. The present invention reduces the risk of damage by providing site having a noble metal on the top surface of the pad, while providing a diffusion barrier to maintain the high conductivity of the metal interconnects. Process steps for forming an I/O site within a substrate are reduced by providing a method for selectively depositing metal layers in a feature formed in the substrate. Since the I/O sites of the present invention may be used for either wire-bond or solder bump connections, this provides increased flexibility for chip interconnection options, while also reducing process costs.

5. 发明授权

US06995475B2 I/C chip suitable for wire bonding 有权
标题翻译： I / C芯片适用于引线键合
公开(公告)号：US06995475B2
公开(公告)日：2006-02-07
申请号：US10666775
申请日：2003-09-18
申请人： Julie C. Biggs , Tien-Jen Cheng , David E. Eichstadt , Lisa A. Fanti , Jonathan H. Griffith , Randolph F. Knarr , Sarah H. Knickerbocker , Kevin S. Petrarca , Roger A. Quon , Wolfgang Sauter , Kamalesh K. Srivastava , Richard P. Volant
发明人： Julie C. Biggs , Tien-Jen Cheng , David E. Eichstadt , Lisa A. Fanti , Jonathan H. Griffith , Randolph F. Knarr , Sarah H. Knickerbocker , Kevin S. Petrarca , Roger A. Quon , Wolfgang Sauter , Kamalesh K. Srivastava , Richard P. Volant
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/04042 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05181 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/4847 , H01L2224/48624 , H01L2224/48644 , H01L2224/48655 , H01L2224/85205 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/04953 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.
摘要翻译：一种在（I / C）芯片中形成引线键合的方法，包括：提供具有导电焊盘的I / C芯片，所述导电焊盘与覆盖所述焊盘的至少一层电介质材料进行引线接合; 通过暴露所述垫的一部分的电介质材料形成开口。在衬垫的暴露表面和开口表面上形成至少第一导电层。在第一导电层上形成种子层; 在种子层上施加光致抗蚀剂; 曝光和显影光致抗蚀剂，其显露出围绕开口的种子层的表面; 去除暴露的种子层; 去除开口中的光致抗蚀剂材料，露出种子层。在开口中的种子层上电镀至少一层第二导电材料层，以及去除围绕开口的电介质层上的第一导电层。本发明还包括所得到的结构。

6. 发明授权

US07572726B2 Method of forming a bond pad on an I/C chip and resulting structure 有权
标题翻译：在I / C芯片上形成接合焊盘的方法和结构
公开(公告)号：US07572726B2
公开(公告)日：2009-08-11
申请号：US11271760
申请日：2005-11-10
申请人： Julie C. Biggs , Tien-Jen Cheng , David E. Eichstadt , Lisa A. Fanti , Jonathan H. Griffith , Randolph F. Knarr , Sarah H. Knickerbocker , Kevin S. Petrarca , Roger A. Quon , Wolfgang Sauter , Kamalesh K. Srivastava , Richard P. Volant
发明人： Julie C. Biggs , Tien-Jen Cheng , David E. Eichstadt , Lisa A. Fanti , Jonathan H. Griffith , Randolph F. Knarr , Sarah H. Knickerbocker , Kevin S. Petrarca , Roger A. Quon , Wolfgang Sauter , Kamalesh K. Srivastava , Richard P. Volant
IPC分类号： H01L21/44
CPC分类号： H01L24/05 , H01L24/03 , H01L24/45 , H01L24/48 , H01L24/85 , H01L2224/04042 , H01L2224/05083 , H01L2224/05147 , H01L2224/05155 , H01L2224/05181 , H01L2224/05624 , H01L2224/05644 , H01L2224/05655 , H01L2224/45144 , H01L2224/48453 , H01L2224/48463 , H01L2224/4847 , H01L2224/48624 , H01L2224/48644 , H01L2224/48655 , H01L2224/85205 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01019 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01076 , H01L2924/01078 , H01L2924/01079 , H01L2924/01327 , H01L2924/04953 , H01L2924/05042 , H01L2924/12042 , H01L2924/14 , H01L2924/00014 , H01L2924/00 , H01L2924/00015
摘要： A method of forming wire bonds in (I/C) chips comprising: providing an I/C chip having a conductive pad for a wire bond with at least one layer of dielectric material overlying the pad; forming an opening through the dielectric material exposing a portion of said pad. Forming at least a first conductive layer on the exposed surface of the pad and on the surface of the opening. Forming a seed layer on the first conductive layer; applying a photoresist over the seed layer; exposing and developing the photoresist revealing the surface of the seed layer surrounding the opening; removing the exposed seed layer; removing the photoresist material in the opening revealing the seed layer. Plating at least one second layer of conductive material on the seed layer in the opening, and removing the first conductive layer on the dielectric layer around the opening. The invention also includes the resulting structure.
摘要翻译：一种在（I / C）芯片中形成引线键合的方法，包括：提供具有导电焊盘的I / C芯片，所述导电焊盘与覆盖所述焊盘的至少一层电介质材料进行引线接合; 通过暴露所述垫的一部分的电介质材料形成开口。在衬垫的暴露表面和开口表面上形成至少第一导电层。在第一导电层上形成种子层; 在种子层上施加光致抗蚀剂; 曝光和显影光致抗蚀剂，其显露出围绕开口的种子层的表面; 去除暴露的种子层; 去除开口中的光致抗蚀剂材料，露出种子层。在开口中的种子层上电镀至少一层第二导电材料层，以及去除围绕开口的电介质层上的第一导电层。本发明还包括所得到的结构。

7. 发明申请

US20080132027A1 PLANAR VERTICAL RESISTOR AND BOND PAD RESISTOR AND RELATED METHOD 失效
标题翻译：平面垂直电阻和焊盘电阻及相关方法
公开(公告)号：US20080132027A1
公开(公告)日：2008-06-05
申请号：US11954782
申请日：2007-12-12
申请人： Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , Kevin S. Petrarca , Anthony K. Stamper , Richard P. Volant
发明人： Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , Kevin S. Petrarca , Anthony K. Stamper , Richard P. Volant
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L23/5228 , H01L23/53238 , H01L23/53295 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.
摘要翻译：公开了避免半导体器件小型化的问题的电阻器及相关方法。在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。这两个实施方案可以单独使用或一起使用。还公开了用于产生电阻器的相关方法。

8. 发明授权

US07528048B2 Planar vertical resistor and bond pad resistor and related method 失效
标题翻译：平面垂直电阻和接合焊盘电阻及相关方法
公开(公告)号：US07528048B2
公开(公告)日：2009-05-05
申请号：US11954782
申请日：2007-12-12
申请人： Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , Kevin S. Petrarca , Anthony K. Stamper , Richard P. Volant
发明人： Douglas D. Coolbaugh , Timothy J. Dalton , Daniel C. Edelstein , Ebenezer E. Eshun , Jeffrey P. Gambino , Kevin S. Petrarca , Anthony K. Stamper , Richard P. Volant
IPC分类号： H01L21/20
CPC分类号： H01L28/20 , H01L23/5228 , H01L23/53238 , H01L23/53295 , H01L27/0688 , H01L2924/0002 , H01L2924/00
摘要： Resistors that avoid the problems of miniaturization of semiconductor devices and a related method are disclosed. In one embodiment, a resistor includes a planar resistor material that extends vertically within at least one metal layer of a semiconductor device. In another embodiment, a resistor includes a resistor material layer extending between a first bond pad and a second bond pad of a semiconductor device. The two embodiments can be used alone or together. A related method for generating the resistors is also disclosed.
摘要翻译：公开了避免半导体器件小型化的问题的电阻器及相关方法。在一个实施例中，电阻器包括在半导体器件的至少一个金属层内垂直延伸的平面电阻器材料。在另一个实施例中，电阻器包括在半导体器件的第一接合焊盘和第二接合焊盘之间延伸的电阻材料层。这两个实施方案可以单独使用或一起使用。还公开了用于产生电阻器的相关方法。

9. 发明授权

US06873027B2 Encapsulated energy-dissipative fuse for integrated circuits and method of making the same 失效
标题翻译：用于集成电路的封装式耗能型熔断器及其制造方法
公开(公告)号：US06873027B2
公开(公告)日：2005-03-29
申请号：US10002447
申请日：2001-10-26
申请人： Timothy J. Dalton , Kevin S. Petrarca , Richard P. Volant
发明人： Timothy J. Dalton , Kevin S. Petrarca , Richard P. Volant
IPC分类号： H01L23/525 , H01L29/00
CPC分类号： H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A laser-programmable fuse structure for an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the fuse structure includes a conductive layer, the conductive layer completing a conductive path between wiring segments in a wiring layer. An organic material is encapsulated underneath the conductive layer, wherein the fuse structure is blown open by application of a beam of laser energy thereto.
摘要翻译：公开了一种用于集成电路器件的激光可编程熔丝结构。在本发明的示例性实施例中，熔丝结构包括导电层，导电层在布线层中的布线段之间完成导电路径。有机材料被封装在导电层下面，其中通过向其施加激光能量而将熔丝结构吹开。

10. 发明授权

US06635506B2 Method of fabricating micro-electromechanical switches on CMOS compatible substrates 有权
标题翻译：在CMOS兼容基板上制造微机电开关的方法
公开(公告)号：US06635506B2
公开(公告)日：2003-10-21
申请号：US10014660
申请日：2001-11-07
申请人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
发明人： Richard P. Volant , John C. Bisson , Donna R. Cote , Timothy J. Dalton , Robert A. Groves , Kevin S. Petrarca , Kenneth J. Stein , Seshadri Subbanna
IPC分类号： H01L2100
CPC分类号： B81C1/00246 , B81B2201/016 , B81B2201/018 , B81B2203/0127 , B81B2207/07 , B81C1/00611 , B81C2201/0122 , B81C2203/0735 , H01G5/40 , H01H59/0009
摘要： A method of fabricating micro-electromechanical switches (MEMS) integrated with conventional semiconductor interconnect levels, using compatible processes and materials is described. The method is based upon fabricating a capacitive switch that is easily modified to produce various configurations for contact switching and any number of metal-dielectric-metal switches. The process starts with a copper damascene interconnect layer, made of metal conductors inlaid in a dielectric. All or portions of the copper interconnects are recessed to a degree sufficient to provide a capacitive air gap when the switch is in the closed state, as well as provide space for a protective layer of, e.g., Ta/TaN. The metal structures defined within the area specified for the switch act as actuator electrodes to pull down the movable beam and provide one or more paths for the switched signal to traverse. The advantage of an air gap is that air is not subject to charge storage or trapping that can cause reliability and voltage drift problems. Instead of recessing the electrodes to provide a gap, one may just add dielectric on or around the electrode. The next layer is another dielectric layer which is deposited to the desired thickness of the gap formed between the lower electrodes and the moveable beam that forms the switching device. Vias are fabricated through this dielectric to provide connections between the metal interconnect layer and the next metal layer which will also contain the switchable beam. The via layer is then patterned and etched to provide a cavity area which contains the lower activation electrodes as well as the signal paths. The cavity is then back-filled with a sacrificial release material. This release material is then planarized with the top of the dielectric, thereby providing a planar surface upon which the beam layer is constructed.
摘要翻译：描述了使用兼容工艺和材料制造与常规半导体互连级别集成的微机电开关（MEMS）的方法。该方法基于制造容易修改以产生用于接触切换和任何数量的金属 - 介电金属开关的各种配置的电容开关。该过程开始于铜镶嵌互连层，由金属导体嵌入电介质中。铜互连的全部或部分凹陷到足以在开关处于闭合状态时提供电容气隙的程度，并为例如Ta / TaN的保护层提供空间。在为开关指定的区域内限定的金属结构用作致动器电极以下拉可移动光束并且提供一个或多个路径用于开关信号横越。气隙的优点是空气不会受到可能导致可靠性和电压漂移问题的电荷储存或捕集。代替使电极凹陷以提供间隙，可以仅在电极上或周围添加电介质。下一层是另一介质层，其被沉积到形成在下电极和形成开关器件的可移动梁之间的间隙的期望厚度上。通过该电介质制造通孔以提供金属互连层和还包含可切换光束的下一个金属层之间的连接。然后对通孔层进行图案化和蚀刻以提供包含下部激活电极以及信号路径的空腔区域。然后用牺牲脱模材料填充空腔。然后将该释放材料与电介质的顶部平坦化，由此提供构造波束层的平坦表面。

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