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1. 发明授权

US5805859A Digital simulator circuit modifier, network, and method 失效
标题翻译：数字模拟器电路修改器，网络和方法
公开(公告)号：US5805859A
公开(公告)日：1998-09-08
申请号：US477149
申请日：1995-06-07
申请人： David J. Giramma , Thomas E. Roth , Oliver W. Kozber , Michael G. Robinson , David K. Johnson
发明人： David J. Giramma , Thomas E. Roth , Oliver W. Kozber , Michael G. Robinson , David K. Johnson
IPC分类号： G06F17/50 , G06F9/455
CPC分类号： G06F17/5022
摘要： Described is a circuit modifier, network, and method for use with an event-driven digital logic simulator for enforcing consistent evaluation of input pin changes at state elements. The invention automatically interposes a fictitious 0-delay defer agent or processor, at the input pin to state elements such as D Flip-Flops. The interposition of the defer agent is handled by the simulator as follows. Defer agents schedule events related to input state changes on a special time or task queue which is not processed until after all other events have been executed for the current time, including any extra iterations caused by 0-delay scheduling activity. Defer agents or processors are placed in a simulation network just prior to one or more of the input pins of state elements, the effect of which is to delay events that normally would propagate to the input pin of a state element until all other normal simulation events are processed. Once the normal simulation events have been executed, the defer events are executed which permits the inputs of the state elements to change after other simulation events have been executed, thereby ensuring consistent evaluation of pin changes at state elements.
摘要翻译：描述了一种与事件驱动的数字逻辑模拟器一起使用的电路修正器，网络和方法，用于在状态元件处执行输入引脚变化的一致评估。本发明在输入引脚处将虚拟的0延迟延迟器或处理器自动地插入诸如D触发器的状态元件。延迟代理的插入由仿真器如下处理。延迟代理程序在特定时间或任务队列上调度与输入状态更改相关的事件，直到所有其他事件已被执行为当前时间，包括由0延迟调度活动引起的任何额外的迭代之后才被处理。延迟代理或处理器位于状态元素的一个或多个输入引脚之前的模拟网络中，其效果是将通常将传播到状态元素的输入引脚的事件延迟，直到所有其他正常模拟事件被处理。一旦执行了正常的模拟事件，执行延迟事件，这允许状态元素的输入在执行其它仿真事件之后改变，从而确保在状态元件处的引脚变化的一致评估。

2. 发明授权

US5726918A Tool, system and method for dynamic timing analysis in a plural-instance digital system simulation 失效
标题翻译：多实例数字系统仿真中动态时序分析的工具，系统和方法
公开(公告)号：US5726918A
公开(公告)日：1998-03-10
申请号：US463881
申请日：1995-06-05
申请人： David J. Giramma , Thomas E. Roth , Oliver W. Kozber
发明人： David J. Giramma , Thomas E. Roth , Oliver W. Kozber
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Described is an invention that provides an efficient selection of timing statements for a logic cell in response to cell pin activity when such cell is implemented as one or more instances of simulator primitives. It does so by defining a first storage structure coupled with a logic processor coupled, in turn to a second storage structure. First storage structure defines plural bitfield arrays corresponding with a cell pin and a possible logic level or state, each bitfield array having an entry for an old or a former state of the pin, a next or new state of that pin and a stable state of that pin and each bitfield array defining an index to one or more memory-based look-up tables defining the number of a timing and/or constraint parameter for the given pin of the logic cell. Such timing parameters describe a delay between two pins of the cell, while such constraint parameters describe timing constraints for the logic cell such as setup times, hold times and minimum pulse width times. In accordance with a preferred embodiment of the invention, a set of rules is enforced by the logic processor during a digital logic simulation run to ensure that appropriate timing and constraint for the logic cell is maintained. Zero-delay timing is used across a collection of instances within a logic cell, thereby to ensure that all timing and constraint analysis is performed at cell boundaries. Timing is evaluated after all simulation activity for a given time frame has ceased, and such is done preferably by scheduling scrubber events that are executed as tasks on a defer queue that is processed at the end of the digital logic simulation activity.
摘要翻译：描述的是当这样的单元被实现为模拟器基元的一个或多个实例时，提供响应于单元引脚活动的逻辑单元的定时语句的有效选择。它通过定义与连接到第二存储结构的逻辑处理器耦合的第一存储结构来实现。第一存储结构定义对应于单元引脚和可能的逻辑电平或状态的多个位字段阵列，每个位字段阵列具有用于引脚的旧状态或前一状态的条目，该引脚的下一个或新状态以及该引脚的稳定状态该引脚和每个位阵列阵列定义一个或多个基于存储器的查找表的索引，其定义逻辑单元的给定引脚的定时和/或约束参数的数量。这种定时参数描述了小区的两个引脚之间的延迟，而这种约束参数描述了逻辑单元的定时约束，例如建立时间，保持时间和最小脉冲宽度时间。根据本发明的优选实施例，逻辑处理器在数字逻辑仿真运行期间强制执行一组规则，以确保维持逻辑单元的适当的定时和约束。在零逻辑单元中的实例集合之间使用零延迟定时，从而确保在单元格边界执行所有定时和约束分析。在给定时间帧的所有模拟活动已停止之后对时序进行评估，并且优选地通过调度作为在数字逻辑模拟活动结束时处理的延迟队列中的任务来执行的擦除器事件来进行定时。

3. 发明授权

US5706476A Method and apparatus for use of the undefined logic state and mixed multiple-state abstractions in digital logic simulation 失效
标题翻译：在数字逻辑仿真中使用未定义逻辑状态和混合多状态抽象的方法和装置
公开(公告)号：US5706476A
公开(公告)日：1998-01-06
申请号：US464390
申请日：1995-06-05
申请人： David J. Giramma
发明人： David J. Giramma
IPC分类号： G06F17/50 , H01L21/70
CPC分类号： G06F17/5022
摘要： Method and apparatus for more efficiently using the undefined logic state and mixed multiple state abstractions is described. The method involves dividing gates into two groups: those that require an 8-state table (either because their inputs are sensitive to 8-state values or their output produces an 8-state value), and those that require only 4-state values (their inputs are insensitive to 8-state values and the output produces only 4-state values). The key to obtaining the advantages of the invention is the choice of the 4-state values. Previously, the 4-state values have been 0, 1, X, and Z. By the invented method and apparatus, the 4-state values are defined instead to be 0S, 1S, XS, and U. In the Multi-value Logic 9-state model (MVL-9), U is defined to be the uninitialized state, and thus it is a state that all instances need to process on their inputs and to produce as an output. The Z (or high-impedance) state, on the other hand, is used only for certain specialized gates--typically tri-state buffers--and so the Z state is used only rarely in digital logic simulation. By shifting the definition of the 4-state abstraction from (0, 1, X, Z) to (0S, 1S, XS, U), almost all gates may be included in the 4-state category, thus allowing higher pin counts for the average digital logic simulation. The invented method and apparatus nevertheless permits the interconnection of 4-state values and 8-state values, while placing the significant overhead of the latter on the rare use thereof. Preferably, both 4-state and 8-state directives--instructions to a downstream gate that tells the gate how to attain a new state--are provided by the invented method and apparatus, and the gate receiving such plural directives effectively decides whether to use the 4-state abstraction or the more expensive 8-state abstraction.
摘要翻译：描述了用于更有效地使用未定义逻辑状态和混合多状态抽象的方法和装置。该方法包括将门分成两组：需要8状态表（由于它们的输入对8状态值敏感或其输出产生8状态值），而仅需要4状态值的那些它们的输入对8状态值不敏感，输出仅产生4态值）。获得本发明优点的关键在于选择4态值。以前，4状态值已经为0，1，X和Z。通过本发明的方法和装置，将4状态值定义为0S，1S，XS和U.在多值逻辑 9状态模型（MVL-9），U被定义为未初始化状态，因此它是所有实例需要处理其输入并产生输出的状态。另一方面，Z（或高阻抗）状态仅用于某些特定的门 - 通常是三态缓冲器，因此Z状态在数字逻辑仿真中很少使用。通过将（0，1，X，Z）的4状态抽象的定义转换为（0S，1S，XS，U），几乎所有的门都可以包含在4状态类别中，因此允许更高的引脚计数平均数字逻辑仿真。然而，本发明的方法和装置允许4状态值和8状态值的互连，同时将后者的显着开销置于其罕见的使用上。优选地，通过本发明的方法和装置提供了4状态指令和8状态指令 - 告诉门如何达到新状态的下游门控指令，并且接收这些多个指令的门有效地决定是否使用 4状态抽象或更昂贵的8状态抽象。

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