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1. 发明授权

US09329846B1 Cooperative program code transformation 有权
标题翻译：合作程序代码转换
公开(公告)号：US09329846B1
公开(公告)日：2016-05-03
申请号：US12951470
申请日：2010-11-22
申请人： David I. August , Kevin C. Fan , Jae Wook Lee , Scott A. Mahlke , Mojtaba Mehrara
发明人： David I. August , Kevin C. Fan , Jae Wook Lee , Scott A. Mahlke , Mojtaba Mehrara
IPC分类号： G06F9/45
CPC分类号： G06F8/443 , G06F9/45525
摘要： Cooperative program code transformation includes receiving a transformation hint request, obtaining a suitable transformation hint, and providing the suitable transformation hint such that it is used to transform at least a portion of the program code and generate optimized code.
摘要翻译：合作程序代码变换包括接收转换提示请求，获得合适的转换提示，以及提供适当的转换提示，使得其用于变换程序代码的至少一部分并生成优化的代码。

2. 发明授权

US06408428B1 Automated design of processor systems using feedback from internal measurements of candidate systems 失效
标题翻译：使用候选系统内部测量的反馈自动设计处理器系统
公开(公告)号：US06408428B1
公开(公告)日：2002-06-18
申请号：US09378290
申请日：1999-08-20
申请人： Michael S. Schlansker , Vinod K. Kathail , Greg Snider , Shail Aditya Gupta , Scott A. Mahlke , Santosh Abraham
发明人： Michael S. Schlansker , Vinod K. Kathail , Greg Snider , Shail Aditya Gupta , Scott A. Mahlke , Santosh Abraham
IPC分类号： G06F1750
CPC分类号： G06F17/5045 , G06F2217/08
摘要： An automated design system for VLIW processors explores a parameterized design space to assist in identifying candidate processor designs that satisfy desired design constraints, such as processor cost and performance. A VLIW synthesis process takes as input a specification of processor parameters and synthesizes a datapath specification, an instruction format design, and a control path specification. The synthesis process also extracts a machine description suitable to re-target a compiler. The re-targeted compiler generates operation issue statistics for an application program or set of programs. Using these statistics, a procedure for searching the design space can extract internal resources utilization information that is used to determine new candidate processors for evaluation.
摘要翻译：用于VLIW处理器的自动化设计系统探索参数化设计空间，以帮助识别满足期望设计约束（例如处理器成本和性能）的候选处理器设计。 VLIW合成过程将处理器参数的规范作为输入，并合成数据路径规范，指令格式设计和控制路径规范。合成过程还提取适合于重新定位编译器的机器描述。重新定位的编译器生成应用程序或程序集的操作问题统计信息。使用这些统计信息，搜索设计空间的过程可以提取用于确定新的候选处理器进行评估的内部资源利用率信息。

3. 发明授权

US06772106B1 Retargetable computer design system 失效
标题翻译：可重定位计算机设计系统
公开(公告)号：US06772106B1
公开(公告)日：2004-08-03
申请号：US09378580
申请日：1999-08-20
申请人： Scott A. Mahlke , Santosh G. Abraham , Vinod K. Kathail
发明人： Scott A. Mahlke , Santosh G. Abraham , Vinod K. Kathail
IPC分类号： G06F944
CPC分类号： G06F11/3461 , G06F8/447
摘要： An automatic and retargetable computer design system is using a combination of simulation and performance prediction to investigate a plurality of target computer systems. A high-level specification and a predetermined application are used by the computer design system to provide inputs into a computer evaluator. The computer evaluator has reference computer system dependent and independent systems for producing a reference representation and dynamic behavior information, respectively, of the application. The reference representation and information are mated to produce further information to drive a simulator. The simulator provides performance information of a reference computer system. The performance information is provided to another computer evaluator, which has a target computer system dependent system for producing a target representation of the application for the plurality of target computer systems. The performance information and the target representation are used by a computer system predictor for quickly estimating the performance information of the plurality of target computer systems in a simulation efficient manner.
摘要翻译：自动和可重定向的计算机设计系统正在使用模拟和性能预测的组合来研究多个目标计算机系统。计算机设计系统使用高级规范和预定应用来向计算机评估器提供输入。计算机评估器具有用于分别用于产生应用的参考表示和动态行为信息的参考计算机系统依赖和独立系统。参考表示和信息被配合以产生进一步的信息来驱动模拟器。模拟器提供参考计算机系统的性能信息。性能信息被提供给另一个计算机评估器，其具有目标计算机系统依赖系统，用于产生用于多个目标计算机系统的应用的目标表示。性能信息和目标表示由计算机系统预测器用于以模拟有效的方式快速估计多个目标计算机系统的性能信息。

4. 发明授权

US06604067B1 Rapid design of memory systems using dilation modeling 失效
标题翻译：使用扩张建模快速设计内存系统
公开(公告)号：US06604067B1
公开(公告)日：2003-08-05
申请号：US09378192
申请日：1999-08-20
申请人： Santosh G. Abraham , Bantwal Ramakrishna Rau , Scott A. Mahlke
发明人： Santosh G. Abraham , Bantwal Ramakrishna Rau , Scott A. Mahlke
IPC分类号： G06F930
CPC分类号： G06F17/5045 , G06F11/3461 , G06F11/3471 , G06F2201/885
摘要： A system is provided which simplifies and speeds up the process of designing a computer system by evaluating the components of the memory hierarchy for any member of a broad family of processors in an application-specific manner. The system uses traces produced by a reference processor in the design space for a particular cache design and characterizes the differences in behavior between the reference processor and an arbitrarily chosen processor. The differences are characterized as a series of dilation parameters which relate to how much the traces would expand because of the substitution of a target processor. In addition, the system characterizes the reference trace using a set of trace parameters that are part of a cache behavior model. The dilation and trace parameters are used to determine the factors for estimating the performance statistics of target processors with specific memory hierarchies.
摘要翻译：提供了一种系统，其通过以应用特定的方式评估广泛的处理器系列的任何成员的存储器层次结构的组件来简化和加速设计计算机系统的过程。该系统使用由设计空间中的参考处理器为特定高速缓存设计生成的跟踪，并描述参考处理器与任意选择的处理器之间的行为差异。这些差异被表征为一系列扩张参数，其涉及由于目标处理器的替代而导致的迹线将扩大多少。此外，系统使用作为缓存行为模型的一部分的一组跟踪参数来表征参考跟踪。扩展和跟踪参数用于确定用于使用特定内存层次结构估计目标处理器的性能统计信息的因素。

5. 发明授权

US5857104A Synthetic dynamic branch prediction 失效
标题翻译：合成动态分支预测
公开(公告)号：US5857104A
公开(公告)日：1999-01-05
申请号：US757038
申请日：1996-11-26
申请人： Balas K. Natarjan , Scott A. Mahlke
发明人： Balas K. Natarjan , Scott A. Mahlke
IPC分类号： G06F9/32 , G06F9/38 , G06F9/45
CPC分类号： G06F9/30094 , G06F8/4451 , G06F8/447 , G06F9/30058 , G06F9/3844 , G06F9/3846
摘要： A compiler includes a branch statistics data analyzer to analyze branch statistics data of a branch instruction to construct a branch predictor function for the branch instruction. A branch prediction instruction generator is coupled to the branch statistics data analyzer to generate at least one prediction instruction to implement the branch predictor function. A main compiling engine is coupled to the branch prediction instruction generator to insert the prediction instruction before the branch instruction. A method of dynamically predicting a branch instruction of a program is also described.
摘要翻译：编译器包括分支统计数据分析器，用于分析分支指令的分支统计数据以构成分支指令的分支预测器功能。分支预测指令发生器耦合到分支统计数据分析器以生成至少一个预测指令来实现分支预测器功能。主编译引擎耦合到分支预测指令发生器，以在分支指令之前插入预测指令。还描述了动态地预测节目的分支指令的方法。

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