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1. 发明授权

US07433977B2 DMAC to handle transfers of unknown lengths 有权
标题翻译： DMAC处理未知长度的传输
公开(公告)号：US07433977B2
公开(公告)日：2008-10-07
申请号：US11563732
申请日：2006-11-28
申请人： David E. Barrow , Clarence V. Roberts
发明人： David E. Barrow , Clarence V. Roberts
IPC分类号： G06F13/28 , G06F13/00
CPC分类号： G06F13/28
摘要： A DMA controller maintains a count of data transferred in each DMA operation, and saves the transferred data count at the end of the DMA operation. The DMA controller may then begin a subsequent DMA transfer operation, without waiting for a processor to read the transferred data count. The transferred data count may be written to memory at an address specified in a transferred data count save address register; may be saved to a transferred data count register dedicated to the DMA channel; or may be saved to a transferred data count register shared between two or more DMA channels. The processor may read the transferred data count and, if applicable, clear the relevant transfer data count register, subsequent to the DMA controller beginning another DMA operation on that DMA channel.
摘要翻译： DMA控制器维护每个DMA操作中传输的数据计数，并在DMA操作结束时保存传输的数据计数。然后，DMA控制器可以开始后续的DMA传输操作，而不必等待处理器读取传送的数据计数。传送的数据计数可以以传送的数据计数保存地址寄存器中指定的地址写入存储器; 可以保存到专用于DMA通道的传送数据计数寄存器; 或者可以将其保存到两个或多个DMA通道之间共享的传送数据计数寄存器。处理器可以在DMA控制器开始DMA通道上的另一个DMA操作之后，读取传送的数据计数，如果适用，清除相关的传输数据计数寄存器。

2. 发明申请

US20080126612A1 DMAC to Handle Transfers of Unknown Lengths 有权
标题翻译： DMAC处理未知长度的转移
公开(公告)号：US20080126612A1
公开(公告)日：2008-05-29
申请号：US11563732
申请日：2006-11-28
申请人： David E. Barrow , Clarence V. Roberts
发明人： David E. Barrow , Clarence V. Roberts
IPC分类号： G06F13/18
CPC分类号： G06F13/28
摘要： A DMA controller maintains a count of data transferred in each DMA operation, and saves the transferred data count at the end of the DMA operation. The DMA controller may then begin a subsequent DMA transfer operation, without waiting for a processor to read the transferred data count. The transferred data count may be written to memory at an address specified in a transferred data count save address register; may be saved to a transferred data count register dedicated to the DMA channel; or may be saved to a transferred data count register shared between two or more DMA channels. The processor may read the transferred data count and, if applicable, clear the relevant transfer data count register, subsequent to the DMA controller beginning another DMA operation on that DMA channel.
摘要翻译： DMA控制器维护每个DMA操作中传输的数据计数，并在DMA操作结束时保存传输的数据计数。然后，DMA控制器可以开始后续的DMA传输操作，而不必等待处理器读取传送的数据计数。传送的数据计数可以以传送的数据计数保存地址寄存器中指定的地址写入存储器; 可以保存到专用于DMA通道的传送数据计数寄存器; 或者可以将其保存到两个或多个DMA通道之间共享的传送数据计数寄存器。处理器可以在DMA控制器开始DMA通道上的另一个DMA操作之后，读取传送的数据计数，如果适用，清除相关的传输数据计数寄存器。

3. 发明授权

US5809091A Timing signal generator for digital communication system 失效
标题翻译：数字通信系统定时信号发生器
公开(公告)号：US5809091A
公开(公告)日：1998-09-15
申请号：US659133
申请日：1996-06-04
申请人： David E. Barrow
发明人： David E. Barrow
IPC分类号： H04J3/06
CPC分类号： H04J3/0691 , H04W56/002
摘要： A timing generator synchronizes a mobile station internal timing with a base station in a TDMA cellular communication system. A random access memory is used to store an event list comprising a series of events which must be executed periodically at precisely timed intervals. Each event in the event list includes an event time and an event code. The events are stored in the random access memory in the order in which they are to occur. The timing generator of the present invention uses a primary counter, a secondary counter, a synchronizing register, a comparator and a signal generator to control the execution of the event in the event list. The primary counter and secondary counter are both clocked at the same rate. The events are read one at a time from the event list into a compare resister. The event time is compared to the value of the secondary counter. When the event time matches the secondary counter value, the event action is passed to the signal generator which decodes and executes the events. The next event is then read into the compared register and the process is repeated until the end of the event list is reached. Once the end of the event list is reached, no further action is taken until the secondary counter is reset, at which time the process is repeated.
摘要翻译：定时发生器将移动台内部定时与TDMA蜂窝通信系统中的基站同步。随机访问存储器用于存储包括必须以精确定时间隔周期性地执行的一系列事件的事件列表。事件列表中的每个事件包括事件时间和事件代码。事件按照它们要发生的顺序存储在随机存取存储器中。本发明的定时发生器使用主计数器，次计数器，同步寄存器，比较器和信号发生器来控制事件列表中的事件的执行。主计数器和次计数器都以相同的速率进行计时。事件从事件列表一次读取到比较寄存器中。将事件时间与次计数器的值进行比较。当事件时间与次计数值匹配时，事件动作被传递到信号发生器，该信号发生器解码并执行事件。然后将下一个事件读入比较的寄存器，并重复该过程，直到达到事件列表的结尾。一旦达到事件列表的结尾，在二级计数器复位之前不再采取进一步措施，此时重复该过程。

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