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1. 发明授权

US08799673B2 Seamlessly encrypting memory regions to protect against hardware-based attacks 有权
标题翻译：无缝加密内存区域以防止基于硬件的攻击
公开(公告)号：US08799673B2
公开(公告)日：2014-08-05
申请号：US12651432
申请日：2009-12-31
申请人： Uday R. Savagaonkar , Ravi Sahita , David Durham , Men Long
发明人： Uday R. Savagaonkar , Ravi Sahita , David Durham , Men Long
IPC分类号： H04L29/06
CPC分类号： G06F12/1408 , G06F12/1441 , G06F2212/1052
摘要： Systems, apparatuses, and methods, and for seamlessly protecting memory regions to protect against hardware-based attacks are disclosed. In one embodiment, an apparatus includes a decoder, control logic, and cryptographic logic. The decoder is to decode a transaction between a processor and memory-mapped input/output space. The control logic is to redirect the transaction from the memory-mapped input/output space to a system memory. The cryptographic logic is to operate on data for the transaction.
摘要翻译：公开了系统，装置和方法，并且用于无缝地保护存储器区域以防止基于硬件的攻击。在一个实施例中，一种装置包括解码器，控制逻辑和加密逻辑。解码器是对处理器和存储器映射的输入/输出空间之间的事务进行解码。控制逻辑是将事务从内存映射的输入/输出空间重定向到系统内存。密码逻辑是对数据进行交易操作。

2. 发明申请

US20090172814A1 DYNAMIC GENERATION OF INTEGRITY MANIFEST FOR RUN-TIME VERIFICATION OF SOFTWARE PROGRAM 有权
标题翻译：软件程序运行验证的完整性更新动态生成
公开(公告)号：US20090172814A1
公开(公告)日：2009-07-02
申请号：US11967928
申请日：2007-12-31
申请人： Hormuzd Khosravi , David Durham , Prashant Dewan , Ravi Sahita , Uday R. Savagaonkar , Men Long
发明人： Hormuzd Khosravi , David Durham , Prashant Dewan , Ravi Sahita , Uday R. Savagaonkar , Men Long
IPC分类号： G06F21/22
CPC分类号： G06F21/64 , G06F21/51
摘要： A measurement engine generates an integrity manifest for a software program and uses it to perform active platform observation. The integrity manifest indicates an integrity check value for a section of the program's code. The measurement engine computes a comparison value on the program's image in memory and determines if the comparison value matches the expected integrity check value. If the values do not match, the program's image is determined to be modified, and appropriate remedial action may be triggered.
摘要翻译：测量引擎为软件程序生成完整性清单，并使用它来执行主动平台观察。完整性清单表示程序代码的一部分的完整性检查值。测量引擎计算内存中程序映像的比较值，并确定比较值是否与预期的完整性校验值相匹配。如果值不匹配，则确定程序的图像被修改，并且可能触发适当的补救动作。

3. 发明授权

US08364973B2 Dynamic generation of integrity manifest for run-time verification of software program 有权
标题翻译：动态生成软件程序的运行时验证的完整性清单
公开(公告)号：US08364973B2
公开(公告)日：2013-01-29
申请号：US11967928
申请日：2007-12-31
申请人： Hormuzd Khosravi , David Durham , Prashant Dewan , Ravi Sahita , Uday R. Savagaonkar , Men Long
发明人： Hormuzd Khosravi , David Durham , Prashant Dewan , Ravi Sahita , Uday R. Savagaonkar , Men Long
IPC分类号： G06F21/00
CPC分类号： G06F21/64 , G06F21/51
摘要： A measurement engine generates an integrity manifest for a software program and uses it to perform active platform observation. The integrity manifest indicates an integrity check value for a section of the program's code. The measurement engine computes a comparison value on the program's image in memory and determines if the comparison value matches the expected integrity check value. If the values do not match, the program's image is determined to be modified, and appropriate remedial action may be triggered.
摘要翻译：测量引擎为软件程序生成完整性清单，并使用它来执行主动平台观察。完整性清单表示程序代码的一部分的完整性检查值。测量引擎计算内存中程序映像的比较值，并确定比较值是否与预期的完整性校验值相匹配。如果值不匹配，则确定程序的图像被修改，并且可能触发适当的补救动作。

4. 发明申请

US20110154059A1 CUMULATIVE INTEGRITY CHECK VALUE (ICV) PROCESSOR BASED MEMORY CONTENT PROTECTION 有权
标题翻译：累积完整性检验值（ICV）处理器内存内容保护
公开(公告)号：US20110154059A1
公开(公告)日：2011-06-23
申请号：US12646028
申请日：2009-12-23
申请人： David Durham , Men Long , Uday R. Savagaonkar
发明人： David Durham , Men Long , Uday R. Savagaonkar
IPC分类号： G06F12/14
CPC分类号： G06F21/79 , G06F21/72
摘要： In general, in one aspect, the disclosure describes a process that includes a cryptographic engine and first and second registers. The cryptographic engine is to encrypt data to be written to memory, to decrypt data read from memory, to generate read integrity check values (ICVs) and write ICVs for memory accesses. The cryptographic engine is also to create a cumulative read ICV and a cumulative write ICV by XORing the generated read ICV and the generated write ICV with a current read MAC and a current write ICV respectively and to validate data integrity by comparing the cumulative read ICV and the cumulative write ICV. The first and second registers are to store the cumulative read and write ICVs respectively at the processor. Other embodiments are described and claimed.
摘要翻译：通常，在一个方面，本公开描述了包括密码引擎和第一和第二寄存器的过程。加密引擎是对要写入存储器的数据进行加密，解密从存储器读取的数据，生成读取完整性检查值（ICV），并为存储器访问写入ICV。密码引擎还通过分别用当前读取的MAC和当前的写入ICV异或生成的读取ICV和产生的写入ICV来创建累积读取ICV和累积写入ICV，并通过比较累积读取ICV和累积写ICV。第一和第二寄存器分别在处理器处存储累积读和写ICV。描述和要求保护其他实施例。

5. 发明申请

US20110161677A1 SEAMLESSLY ENCRYPTING MEMORY REGIONS TO PROTECT AGAINST HARDWARE-BASED ATTACKS 有权
标题翻译：无缝加密存储区域防范基于硬件的攻击
公开(公告)号：US20110161677A1
公开(公告)日：2011-06-30
申请号：US12651432
申请日：2009-12-31
申请人： Uday R. Savagaonkar , Ravi Sahita , David Durham , Men Long
发明人： Uday R. Savagaonkar , Ravi Sahita , David Durham , Men Long
IPC分类号： G06F12/14
CPC分类号： G06F12/1408 , G06F12/1441 , G06F2212/1052
摘要： Systems, apparatuses, and methods, and for seamlessly protecting memory regions to protect against hardware-based attacks are disclosed. In one embodiment, an apparatus includes a decoder, control logic, and cryptographic logic. The decoder is to decode a transaction between a processor and memory-mapped input/output space. The control logic is to redirect the transaction from the memory-mapped input/output space to a system memory. The cryptographic logic is to operate on data for the transaction.
摘要翻译：公开了系统，装置和方法，并且用于无缝地保护存储器区域以防止基于硬件的攻击。在一个实施例中，一种装置包括解码器，控制逻辑和加密逻辑。解码器是对处理器和存储器映射的输入/输出空间之间的事务进行解码。控制逻辑是将事务从存储器映射的输入/输出空间重定向到系统存储器。密码逻辑是对数据进行交易操作。

6. 发明授权

US09092644B2 Method and system for protecting memory information in a platform 有权
标题翻译：保护平台内存信息的方法和系统
公开(公告)号：US09092644B2
公开(公告)日：2015-07-28
申请号：US13976935
申请日：2011-12-28
申请人： Alpa T. Narendra Trivedi , David M. Durham , Men Long , Siddhartha Chhabra , Uday R. Savagaonkar , Carlos V. Rozas
发明人： Alpa T. Narendra Trivedi , David M. Durham , Men Long , Siddhartha Chhabra , Uday R. Savagaonkar , Carlos V. Rozas
IPC分类号： G06F21/64 , H04L9/06 , G06F12/14 , G06F21/78 , G06F21/79
CPC分类号： G06F21/64 , G06F12/1408 , G06F21/78 , G06F21/79 , H04L9/0643 , H04L2209/12
摘要： A method and system to provide an effective, scalable and yet low-cost solution for Confidentiality, Integrity and Replay protection for sensitive information stored in a memory and prevent an attacker from observing and/or modifying the state of the system. In one embodiment of the invention, the system has strong hardware protection for its memory contents via XTS-tweak mode of encryption where the tweak is derived based on “Global and Local Counters”. This scheme offers to enable die-area efficient Replay protection for any sized memory by allowing multiple counter levels and facilitates using small counter-sizes to derive the “tweak” used in the XTS encryption without sacrificing cryptographic strength.
摘要翻译：一种方法和系统，为存储在存储器中的敏感信息提供有效，可扩展且低成本的保密性，完整性和重放保护解决方案，并防止攻击者观察和/或修改系统的状态。在本发明的一个实施例中，系统通过经由XTS调整加密模式对其存储器内容具有强大的硬件保护，其中基于“全局和本地计数器”导出调整。该方案提供了通过允许多个计数器级别为任何大小的存储器提供芯片区域高效的重放保护，并有助于使用小型计数器来导出XTS加密中使用的“调整”，而不会牺牲加密强度。

7. 发明申请

US20140101461A1 PARALLELIZED COUNTER TREE WALK FOR LOW OVERHEAD MEMORY REPLAY PROTECTION 有权
标题翻译：并行平衡计数器用于低过载存储器重放保护
公开(公告)号：US20140101461A1
公开(公告)日：2014-04-10
申请号：US13646105
申请日：2012-10-05
申请人： Siddhartha Chhabra , Uday R. Savagaonkar , David M. Durham , Niranjan L. Cooray , Men Long , Carlos V. Rozas , Alpa T. Narendra Trivedi
发明人： Siddhartha Chhabra , Uday R. Savagaonkar , David M. Durham , Niranjan L. Cooray , Men Long , Carlos V. Rozas , Alpa T. Narendra Trivedi
IPC分类号： G06F12/14
CPC分类号： G06F12/1408 , G06F21/71
摘要： A processor includes a memory encryption engine that provides replay and confidentiality protections to a memory region. The memory encryption engine performs low-overhead parallelized tree walks along a counter tree structure. The memory encryption engine upon receiving an incoming read request for the protected memory region, performs a dependency check operation to identify dependency between the incoming read request and an in-process request and to remove the dependency when the in-process request is a read request that is not currently suspended.
摘要翻译：处理器包括为存储器区域提供重放和保密性保护的存储器加密引擎。存储器加密引擎沿着计数器树结构执行低架构并行化的树行走。存储器加密引擎在接收到对受保护的存储器区域的传入读取请求时，执行依赖性检查操作以识别传入的读取请求与进程内请求之间的依赖关系，并且当进程内请求是读取请求时，去除依赖关系目前尚未暂停。

8. 发明申请

US20160179702A1 Memory Encryption Engine Integration 有权
标题翻译：内存加密引擎集成
公开(公告)号：US20160179702A1
公开(公告)日：2016-06-23
申请号：US14581928
申请日：2014-12-23
申请人： Siddhartha Chhabra , Uday R. Savagaonkar , Men Long , Edgar Borrayo , Alpa T. Narendra Trivedi , Carlos Ornelas
发明人： Siddhartha Chhabra , Uday R. Savagaonkar , Men Long , Edgar Borrayo , Alpa T. Narendra Trivedi , Carlos Ornelas
IPC分类号： G06F12/14 , G06F9/54
CPC分类号： G06F12/1408 , G06F9/546 , G06F13/16 , G06F13/1605 , G06F21/72 , G06F2212/1052 , Y02D10/14
摘要： Memory encryption engine (MEE) integration technologies are described. A processor can include a processor core and an arbiter of a MEE system coupled to the processor core. The arbiter can receive a first contending request from a first queue and a second contending request from a second queue. The arbiter can further select the first queue to communicate the first message to an MEE of the MEE system or the second queue to communicate the second message to the MEE in view of arbitration criteria. The arbiter can further communicate the selected first message or the selected second message to the MEE.
摘要翻译：描述内存加密引擎（MEE）集成技术。处理器可以包括处理器核心和耦合到处理器核心的MEE系统的仲裁器。仲裁器可以从第一个队列接收第一个有争议的请求，并从第二个队列接收第二个有争议的请求。鉴于仲裁标准，仲裁器可以进一步选择第一队列以将第一消息传送到MEE系统的MEE或第二队列，以将第二消息传送给MEE。仲裁器可以进一步将所选择的第一消息或所选择的第二消息传送给MEE。

9. 发明申请

US20140040632A1 LOW-OVERHEAD CRYPTOGRAPHIC METHOD AND APPARATUS FOR PROVIDING MEMORY CONFIDENTIALITY, INTEGRITY AND REPLAY PROTECTION 有权
标题翻译：用于提供记忆保密性，完整性和重复保护的低成本克隆方法和设备
公开(公告)号：US20140040632A1
公开(公告)日：2014-02-06
申请号：US13976930
申请日：2011-12-28
申请人： Siddhartha Chhabra , Uday R. Savagaonkar , Carlos V. Rozas , Alpa T. Narendra Trivedi , Men Long , David M. Durham
发明人： Siddhartha Chhabra , Uday R. Savagaonkar , Carlos V. Rozas , Alpa T. Narendra Trivedi , Men Long , David M. Durham
IPC分类号： G06F21/64
CPC分类号： G06F21/64 , G06F12/1408 , G06F21/00 , G06F21/77
摘要： A method and system to provide a low-overhead cryptographic scheme that affords memory confidentiality, integrity and replay-protection by removing the critical read-after-write dependency between the various levels of the cryptographic tree. In one embodiment of the invention, the cryptographic processing of a child node can be pipelined with that of the parent nodes. This parallelization provided by the invention results in an efficient utilization of the cryptographic pipeline, enabling significantly lower performance overheads.
摘要翻译：一种提供低开销加密方案的方法和系统，其通过去除加密树的各个级别之间的关键读后依赖关系来提供内存机密性，完整性和重放保护。在本发明的一个实施例中，子节点的密码处理可以与母节点的密码处理流水线化。由本发明提供的这种并行化导致密码流水线的有效利用，能够显着降低性能开销。

10. 发明申请

US20160182223A1 Encryption Interface 有权
标题翻译：加密界面
公开(公告)号：US20160182223A1
公开(公告)日：2016-06-23
申请号：US14581946
申请日：2014-12-23
申请人： Eugene M. Kishinevsky , Uday R. Savagaonkar , Alpa T. Narendra Trivedi , Siddhartha Chhabra , Baiju V. Patel , Men Long , Kirk S. Yap , David M. Durham
发明人： Eugene M. Kishinevsky , Uday R. Savagaonkar , Alpa T. Narendra Trivedi , Siddhartha Chhabra , Baiju V. Patel , Men Long , Kirk S. Yap , David M. Durham
IPC分类号： H04L9/06 , G06F12/14 , G06F21/62
CPC分类号： H04L9/0631 , G06F12/1408 , G06F12/1425 , G06F21/602 , G06F21/85 , G06F2212/1052 , G06F2212/402 , G09C1/00 , H04L2209/125 , Y02D10/13
摘要： Encryption interface technologies are described. A processor can include a system agent, an encryption interface, and a memory controller. The system agent can communicate data with a hardware functional block. The encryption interface can be coupled between the system agent and a memory controller. The encryption interface can receive a plaintext request from the system agent, encrypt the plaintext request to obtain an encrypted request, and communicate the encrypted request to the memory controller. The memory controller can communicate the encrypted request to a main memory of the computing device.
摘要翻译：描述加密接口技术。处理器可以包括系统代理，加密接口和存储器控制器。系统代理可以与硬件功能块通信数据。加密接口可以耦合在系统代理和存储器控制器之间。加密接口可以从系统代理接收明文请求，加密明文请求以获得加密请求，并将加密的请求传送到存储器控制器。存储器控制器可以将加密的请求传送到计算设备的主存储器。

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