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1. 发明申请

US20050007216A1 MOS ESD CDM clamp with integral substrate injection guardring and method for fabrication 有权
标题翻译：具有集成衬底注入防护罩的MOS ESD CDM夹具及其制造方法
公开(公告)号：US20050007216A1
公开(公告)日：2005-01-13
申请号：US10609920
申请日：2003-06-30
申请人： David Baldwin , Joseph Devore , Robert Steinhoff , Jonathan Brodsky
发明人： David Baldwin , Joseph Devore , Robert Steinhoff , Jonathan Brodsky
IPC分类号： H01L27/02 , H01L29/06 , H01L29/423 , H01P1/20
CPC分类号： H01L29/0692 , H01L27/0266 , H01L29/4238
摘要： The present invention includes a MOS device (100) that has a P-type substrate (102) and an N-type drain region (104) formed within the substrate (102). An annular N-type source region (106) generally surrounds the drain region (104). The source region (106) serves as both the source for the MOS device (100) and a sacrificial collector guard ring for an electrostatic discharge protection circuit. An annular gate region (110) generally surrounds the drain region (104) and is electrically insulated from the drain region (104) and electrically connected to the source region (106). An annular P-type bulk region (108) generally surrounds the source region (106) and is electrically connected to the source region (106).
摘要翻译：本发明包括具有形成在基板（102）内的P型基板（102）和N型漏极区（104）的MOS器件（100）。环形N型源极区域（106）通常围绕漏极区域（104）。源极区域（106）用作MOS器件（100）的源极和用于静电放电保护电路的牺牲集电极保护环。环形栅极区域（110）通常围绕漏极区域（104）并且与漏极区域（104）电绝缘并且电连接到源极区域（106）。环形P型体区域（108）通常围绕源极区域（106）并且电连接到源极区域（106）。

2. 发明申请

US20060271323A1 Method evaluating threshold level of a data cell in a memory device 有权
标题翻译：方法评估存储器件中数据单元的阈值水平
公开(公告)号：US20060271323A1
公开(公告)日：2006-11-30
申请号：US11139172
申请日：2005-05-28
申请人： David Baldwin , Eric Blackall , Joseph Devore , Ross Teggatz
发明人： David Baldwin , Eric Blackall , Joseph Devore , Ross Teggatz
IPC分类号： G06F19/00
CPC分类号： G11C16/34
摘要： A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order: (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.
摘要翻译：一种评估存储器件中的数据单元的阈值的方法，包括与所述数据单元耦合的编程轨迹，用于接收在所述数据单元中设置存储的信号电平的编程信号，并且响应于读取信号以指示所读取的位置处存储的信号 ; 包括以下步骤：（a）没有特定的顺序：（1）选择测试阈值信号; 和（2）以非读取级别设置读取信号; （b）将测试阈值信号应用于编程轨迹; （c）在读取电平和非读取电平之间循环读取信号，同时当读取信号处于读取电平时，将测试阈值信号施加到编程轨迹，以在读取轨迹处呈现至少两个测试信号; 和（d）循环时，观察至少两个测试信号是否表现出大于预定量的差。

3. 发明申请

US20070240026A1 Method Evaluating Threshold Level of a Data Cell in a Memory Device 有权
标题翻译：方法评估存储器件中数据单元的阈值级别
公开(公告)号：US20070240026A1
公开(公告)日：2007-10-11
申请号：US11755891
申请日：2007-05-31
申请人： David Baldwin , Eric Blackall , Joseph Devore , Ross Teggatz
发明人： David Baldwin , Eric Blackall , Joseph Devore , Ross Teggatz
IPC分类号： G01R31/28
CPC分类号： G11C16/34
摘要： A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order: (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.
摘要翻译：一种评估存储器件中的数据单元的阈值的方法，包括与所述数据单元耦合的编程轨迹，用于接收在所述数据单元中设置存储的信号电平的编程信号，并且响应于读取信号以指示所读取的位置处存储的信号 ; 包括以下步骤：（a）没有特定的顺序：（1）选择测试阈值信号; 和（2）以非读取级别设置读取信号; （b）将测试阈值信号应用于编程轨迹; （c）在读取电平和非读取电平之间循环读取信号，同时当读取信号处于读取电平时，将测试阈值信号施加到编程轨迹，以在读取轨迹处呈现至少两个测试信号; 和（d）循环时，观察至少两个测试信号是否表现出大于预定量的差。

4. 发明授权

US07516037B2 Method evaluating threshold level of a data cell in a memory device 有权
标题翻译：方法评估存储器件中数据单元的阈值水平
公开(公告)号：US07516037B2
公开(公告)日：2009-04-07
申请号：US11755891
申请日：2007-05-31
申请人： David John Baldwin , Eric Blackall , Joseph Devore , Ross E. Teggatz
发明人： David John Baldwin , Eric Blackall , Joseph Devore , Ross E. Teggatz
IPC分类号： G06F15/00
CPC分类号： G11C16/34
摘要： A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order; (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.
摘要翻译：一种评估存储器件中的数据单元的阈值的方法，包括与所述数据单元耦合的编程轨迹，用于接收在所述数据单元中设置存储的信号电平的编程信号，并且响应于读取信号以指示所读取的位置处存储的信号 ; 包括以下步骤：（a）没有特别的顺序; （1）选择测试阈值信号; 和（2）以非读取级别设置读取信号; （b）将测试阈值信号应用于编程轨迹; （c）在读取电平和非读取电平之间循环读取信号，同时当读取信号处于读取电平时，将测试阈值信号施加到编程轨迹，以在读取轨迹处呈现至少两个测试信号; 和（d）循环时，观察至少两个测试信号是否表现出大于预定量的差。

5. 发明授权

US6121760A Turn-on controller for switch-mode regulator 失效
标题翻译：开关型稳压器的开启控制器
公开(公告)号：US6121760A
公开(公告)日：2000-09-19
申请号：US210224
申请日：1994-03-17
申请人： Andrew Marshall , Joseph Devore
发明人： Andrew Marshall , Joseph Devore
IPC分类号： H02M3/157 , G05F1/56
CPC分类号： H02M3/157
摘要： A switch-mode power regulator includes a turn-on controller 52 to limit, during a fixed period of time, the initial current passing through the regulator following turn-on. During this time period the storage elements of the regulator must achieve an acceptable level of stability without excessive current flow. Turn-on controller 52 comprises a divider 72 which clocks zeroes along the length of a shift register 74 which is initially preset to all ones. The outputs of the shift register are coupled to a decoder 76, whose input signals are sequentially steered to its output under the control of a counter 70. The output signal from decoder 76 functions as the power regulator switching signal from turn-on controller 52. Counter 70 cycles many times for each data shift of shift register 74. Thus, turn-on controller 52 generates a train of negative pulses which increase in length monotonically for the duration of the sequence. In one embodiment, the first two data inputs of decoder 76 are grounded, thereby providing a fixed minimum pulse width at the onset of the sequence. In another embodiment, the last two data inputs of decoder 76 are tied to logic supply voltage, thereby preventing cycle skipping.
摘要翻译：开关模式功率调节器包括接通控制器52，以在固定的时间段内限制在导通之后通过调节器的初始电流。在此期间，调节器的存储元件必须达到可接受的稳定水平，而不会有过大的电流流动。接通控制器52包括分频器72，该分频器72沿着移位寄存器74的长度对零进行定时，该移位寄存器74最初被预设为全部移位寄存器。移位寄存器的输出耦合到解码器76，解码器76的输入信号在计数器70的控制下被顺序转向其输出。来自解码器76的输出信号用作来自开启控制器52的功率调节器切换信号。对于移位寄存器74的每个数据移位，计数器70循环多次。因此，导通控制器52产生一串负的脉冲，其长度在序列的持续时间内单调增加。在一个实施例中，解码器76的前两个数据输入端接地，从而在序列开始时提供固定的最小脉冲宽度。在另一个实施例中，解码器76的最后两个数据输入被连接到逻辑电源电压，从而防止循环跳过。

6. 发明授权

US07269528B2 Method evaluating threshold level of a data cell in a memory device 有权
标题翻译：方法评估存储器件中数据单元的阈值水平
公开(公告)号：US07269528B2
公开(公告)日：2007-09-11
申请号：US11139172
申请日：2005-05-28
申请人： David John Baldwin , Eric Blackall , Joseph Devore , Ross E. Teggatz
发明人： David John Baldwin , Eric Blackall , Joseph Devore , Ross E. Teggatz
IPC分类号： G06F15/00
CPC分类号： G11C16/34
摘要： A method evaluating threshold of a data cell in a memory device including a programming locus coupled with the data cell for receiving a programming signal setting a stored signal level in the data cell and responding to a read signal to indicate the stored signal at a read locus; includes the steps of: (a) in no particular order: (1) selecting a test threshold signal; and (2) setting a read signal at a non-read level; (b) applying the test threshold signal to the programming locus; (c) cycling the read signal between a read level and a non-read level while applying the test threshold signal to the programming locus to present at least two test signals at the read locus when the read signal is at the read level; and (d) while cycling, observing whether the at least two test signals manifest a difference greater than a predetermined amount.
摘要翻译：一种评估存储器件中的数据单元的阈值的方法，包括与所述数据单元耦合的编程轨迹，用于接收在所述数据单元中设置存储的信号电平的编程信号，并且响应于读取信号以指示所读取的位置处存储的信号 ; 包括以下步骤：（a）没有特定的顺序：（1）选择测试阈值信号; 和（2）以非读取级别设置读取信号; （b）将测试阈值信号应用于编程轨迹; （c）在读取电平和非读取电平之间循环读取信号，同时当读取信号处于读取电平时，将测试阈值信号施加到编程轨迹，以在读取轨迹处呈现至少两个测试信号; 和（d）循环时，观察至少两个测试信号是否表现出大于预定量的差。

7. 发明申请

US20060261793A1 Circuits, devices and methods for regulator minimum load control 有权
公开(公告)号：US20060261793A1
公开(公告)日：2006-11-23
申请号：US11132750
申请日：2005-05-18
申请人： John Carpenter , Brett Thompsen , Benjamin Amey , Zhihong You , Joseph Devore
发明人： John Carpenter , Brett Thompsen , Benjamin Amey , Zhihong You , Joseph Devore
IPC分类号： G05F1/00
CPC分类号： G05F1/618
摘要： Systems, methods and circuits for regulator minimum load control. In one particular case, a system is provided that includes a load control circuit and a switched load. The load control circuit includes a reference current, and a sense current representative of a load current. In addition, the load control circuit includes a comparator circuit that drives a control signal in response to a comparison between the reference current and the sense current. The switched load is electrically coupled to a load voltage signal to provide loading to the load voltage signal. The switched load is operable to switch between a first loading factor and a second loading factor in response to the control signal.

8. 发明授权

US07133268B2 Current control via a variable voltage snubbing network 有权
标题翻译：通过可变电压缓冲网络进行电流控制
公开(公告)号：US07133268B2
公开(公告)日：2006-11-07
申请号：US10725164
申请日：2003-12-01
申请人： Rex M. Teggatz , Wayne Tien-Feng Chen , Joseph Devore
发明人： Rex M. Teggatz , Wayne Tien-Feng Chen , Joseph Devore
IPC分类号： H02H3/20 , H02H9/04
CPC分类号： B60T8/36
摘要： System and method for controlling current across a load. A preferred embodiment comprises a current varying circuit (such as current varying circuit 525) that can create a sequence of voltage drops in a driver circuit (such as the driver circuit 505) coupled to an inductive load (such as the inductive load 535). By initially producing a large voltage drop and then stepping the voltage drop down gradually, the current in the inductive load can be rapidly removed without producing a current undershoot, which, in certain applications, can result in unwanted noise and vibration.
摘要翻译：用于控制负载电流的系统和方法。优选实施例包括电流变化电路（例如电流变化电路525），其可以在耦合到感性负载（例如感性负载535）的驱动器电路（例如驱动器电路505）中产生一系列电压降。通过初始产生大的电压降，然后逐渐降低电压降，电感负载中的电流可以快速去除，而不产生电流下冲，在某些应用中，这可能导致不必要的噪声和振动。

9. 发明申请

US20050117265A1 Current control via a variable voltage snubbing network 有权
标题翻译：通过可变电压缓冲网络进行电流控制
公开(公告)号：US20050117265A1
公开(公告)日：2005-06-02
申请号：US10725164
申请日：2003-12-01
申请人： Rex Teggatz , Wayne Tien-Feng Chen , Joseph Devore
发明人： Rex Teggatz , Wayne Tien-Feng Chen , Joseph Devore
IPC分类号： B60T8/36 , H02H3/20
CPC分类号： B60T8/36
摘要： System and method for controlling current across a load. A preferred embodiment comprises a current varying circuit (such as current varying circuit 525) that can create a sequence of voltage drops in a driver circuit (such as the driver circuit 505) coupled to an inductive load (such as the inductive load 535). By initially producing a large voltage drop and then stepping the voltage drop down gradually, the current in the inductive load can be rapidly removed without producing a current undershoot, which, in certain applications, can result in unwanted noise and vibration.
摘要翻译：用于控制负载电流的系统和方法。优选实施例包括电流变化电路（例如电流变化电路525），其可以在耦合到感性负载（例如感性负载535）的驱动器电路（例如驱动器电路505）中产生一系列电压降。通过初始产生大的电压降，然后逐渐降低电压降，电感负载中的电流可以快速去除，而不产生电流下冲，在某些应用中，这可能导致不必要的噪声和振动。

10. 发明授权

US5432741A Circuit for permanently disabling EEPROM programming 失效
标题翻译：用于永久禁用EEPROM编程的电路
公开(公告)号：US5432741A
公开(公告)日：1995-07-11
申请号：US210205
申请日：1994-03-17
申请人： Joseph Devore , Andrew Marshall
发明人： Joseph Devore , Andrew Marshall
IPC分类号： G11C17/00 , G06F21/02 , G06F21/24 , G11C16/02 , G11C16/22 , G11C11/34
CPC分类号： G11C16/22
摘要： A circuit for programming an EEPROM 42 which is used to provide trim adjustment for an integrated circuit (IC). The programming circuit provides the capability of programming the EEPROM 42 indefinitely, employing interfaces which are available even after the IC is packaged and encapsulated. Furthermore, it provides the manufacturer or enduser the capability of disabling the programming function permanently, to thereby prevent any inadvertent modifications of the EEPROM 42 data. The programming circuit includes a one-bit EEPROM 32, a nonvolatile memory element which retains its programmed logic state whether or not it is powered up. EEPROM 32 is set during final probe test by the application of a voltage to a probe pad 30 coupled to its set input terminal. Probe pad 30 is exposed such that it may be contacted by a probe prior to IC encapsulation, but is inaccessible after encapsulation. So long as EEPROM 32 is set, EEPROM 42 may be modified upon receipt of a unique address from the system data bus followed by programming data for EEPROM 42. When EEPROM 32 is reset, the programming function of EEPROM 42 is permanently disabled. In a first embodiment, EEPROM 32 is reset by setting a predetermined one of the EEPROM 42 bits to a specified logic state. In a second embodiment, EEPROM 32 is reset by the receipt of another unique address decode from the system data bus.
摘要翻译：用于编程EEPROM 42的电路，其用于为集成电路（IC）提供调整调整。编程电路提供了无限期编程EEPROM 42的能力，采用甚至在IC封装和封装后即使可用的接口。此外，它为制造商或终端用户提供永久禁用编程功能的能力，从而防止对EEPROM 42数据的任何不经意的修改。编程电路包括一位EEPROM32，非易失性存储器元件，其保持其编程的逻辑状态，不管其是否被加电。在最终探针测试期间，通过向耦合到其设置的输入端子的探针焊盘30施加电压来设置EEPROM 32。探针垫30被暴露，使得其可以在IC封装之前被探针接触，但在封装之后是不可接近的。只要设置了EEPROM32，就可以从系统数据总线接收到唯一的地址，随后编程EEPROM 42的编程数据来修改EEPROM 42。当EEPROM32复位时，EEPROM 42的编程功能被永久地禁用。在第一实施例中，通过将EEPROM 42位中的预定的一个设置为指定的逻辑状态来复位EEPROM32。在第二实施例中，通过从系统数据总线接收另一唯一的地址解码来复位EEPROM32。

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