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1. 发明申请

US20060282605A1 High-speed internal bus architecture for an integrated circuit 有权
标题翻译：用于集成电路的高速内部总线架构
公开(公告)号：US20060282605A1
公开(公告)日：2006-12-14
申请号：US11149553
申请日：2005-06-10
申请人： David Avishai , Eliezer Weitz , Yehiel Engel , Raanan Gewirtzman
发明人： David Avishai , Eliezer Weitz , Yehiel Engel , Raanan Gewirtzman
IPC分类号： G06F13/36
CPC分类号： G06F13/36 , G06F13/4059
摘要： An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interface units for interfacing with the modules of the ASIC and at least one basic modular unit coupled to the interface units for allowing simultaneous data transfers between the interface units. Each of the basic modular units has an upload unit for transferring upstream data, and a download unit for transferring downstream data.
摘要翻译：内部总线架构，能够提供与集成电路（例如专用集成电路（ASIC））连接的模块之间的高速互连和互通。内部总线架构包括用于与ASIC的模块进行接口的多个接口单元和耦合到接口单元的至少一个基本模块单元，用于允许在接口单元之间同时进行数据传输。每个基本模块单元具有用于传送上游数据的上传单元和用于传送下游数据的下载单元。

2. 发明授权

US07370127B2 High-speed internal bus architecture for an integrated circuit 有权
标题翻译：用于集成电路的高速内部总线架构
公开(公告)号：US07370127B2
公开(公告)日：2008-05-06
申请号：US11149553
申请日：2005-06-10
申请人： David Avishai , Eliezer Weitz , Yehiel Engel , Raanan Gewirtzman
发明人： David Avishai , Eliezer Weitz , Yehiel Engel , Raanan Gewirtzman
IPC分类号： G06F3/00
CPC分类号： G06F13/36 , G06F13/4059
摘要： An internal bus architecture capable of providing high speed inter-connection and inter-communication between modules connected in an integrated circuit such as an application specific integrated circuit (ASIC). The internal bus architecture includes multiple interface units for interfacing with the modules of the ASIC and at least one basic modular unit coupled to the interface units for allowing simultaneous data transfers between the interface units. Each of the basic modular units has an upload unit for transferring upstream data, and a download unit for transferring downstream data.
摘要翻译：内部总线架构，能够提供与集成电路（例如专用集成电路（ASIC））连接的模块之间的高速互连和互通。内部总线架构包括用于与ASIC的模块进行接口的多个接口单元和耦合到接口单元的至少一个基本模块单元，用于允许在接口单元之间同时进行数据传输。每个基本模块单元具有用于传送上游数据的上传单元和用于传送下游数据的下载单元。

3. 发明授权

US08948594B2 Enhanced passive optical network (PON) processor 有权
标题翻译：增强型无源光网络（PON）处理器
公开(公告)号：US08948594B2
公开(公告)日：2015-02-03
申请号：US12616553
申请日：2009-11-11
申请人： Eliezer Weitz , Gil Levy , David Avishai , Eli Elmoalem , Moti Kurnick , Gal Sitton
发明人： Eliezer Weitz , Gil Levy , David Avishai , Eli Elmoalem , Moti Kurnick , Gal Sitton
IPC分类号： H04J14/08 , H04B10/272 , H04L12/861 , H04Q11/00
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9073 , H04Q11/0067 , H04Q11/0071
摘要： A method for processing data flows of a plurality of passive optical network (PON) operating modes, the method is performed by an optical network unit (ONU). The method comprises processing upstream data flows of said plurality of PON operating modes; and processing downstream data flows of the plurality of PON operating modes. The plurality of PON operating modes include at least a Gigabit PON (GPON) mode, a broadband PON (BPON) mode, and an Ethernet PON (EPON).
摘要翻译：一种用于处理多个无源光网络（PON）操作模式的数据流的方法，该方法由光网络单元（ONU）执行。该方法包括处理所述多个PON操作模式的上游数据流; 以及处理多个PON操作模式的下游数据流。多个PON操作模式至少包括千兆PON（GPON）模式，宽带PON（BPON）模式和以太网PON（EPON）。

4. 发明申请

US20100067908A1 Enhanced Passive Optical Network (PON) Processor 有权
标题翻译：增强型无源光网络（PON）处理器
公开(公告)号：US20100067908A1
公开(公告)日：2010-03-18
申请号：US12616553
申请日：2009-11-11
申请人： Eliezer Weitz , Gil Levy , David Avishai , Eli Elmoalem , Moti Kurnick , Gal Sitton
发明人： Eliezer Weitz , Gil Levy , David Avishai , Eli Elmoalem , Moti Kurnick , Gal Sitton
IPC分类号： H04B10/20
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9073 , H04Q11/0067 , H04Q11/0071
摘要： A method for processing data flows of a plurality of passive optical network (PON) operating modes, the method is performed by an optical network unit (ONU). The method comprises processing upstream data flows of said plurality of PON operating modes; and processing downstream data flows of the plurality of PON operating modes. The plurality of PON operating modes include at least a Gigabit PON (GPON) mode, a broadband PON (BPON) mode, and an Ethernet PON (EPON).
摘要翻译：一种用于处理多个无源光网络（PON）操作模式的数据流的方法，该方法由光网络单元（ONU）执行。该方法包括处理所述多个PON操作模式的上游数据流; 以及处理多个PON操作模式的下游数据流。多个PON操作模式至少包括千兆PON（GPON）模式，宽带PON（BPON）模式和以太网PON（EPON）。

5. 发明授权

US07643753B2 Enhanced passive optical network (PON) processor 有权
标题翻译：增强型无源光网络（PON）处理器
公开(公告)号：US07643753B2
公开(公告)日：2010-01-05
申请号：US11238022
申请日：2005-09-29
申请人： Eliezer Weitz , Gil Levy , David Avishai , Eli Elmoalem , Moti Kurnick , Gal Sitton
发明人： Eliezer Weitz , Gil Levy , David Avishai , Eli Elmoalem , Moti Kurnick , Gal Sitton
IPC分类号： H04J14/00
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9073 , H04Q11/0067 , H04Q11/0071
摘要： An enhanced passive optical network (PON) processor adapted to serve a plurality of PON applications is disclosed. The PON processor is a highly integrated communications processor that can operate in different PON modes including, but not limited to, a gigabit PON (GPON), a broadband PON (BPON), an Ethernet PON (EPON), or any combination thereof. In an embodiment of the present invention the provided PON is fabricated on a single integrated circuit (IC).
摘要翻译：公开了一种适用于服务多个PON应用的增强型无源光网络（PON）处理器。 PON处理器是可以在不同PON模式下工作的高度集成的通信处理器，包括但不限于千兆位PON（GPON），宽带PON（BPON），以太网PON（EPON）或其任何组合。在本发明的实施例中，所提供的PON被制造在单个集成电路（IC）上。

6. 发明申请

US20070070997A1 Enhanced passive optical network (PON) processor 有权
标题翻译：增强型无源光网络（PON）处理器
公开(公告)号：US20070070997A1
公开(公告)日：2007-03-29
申请号：US11238022
申请日：2005-09-29
申请人： Eliezer Weitz , Gil Levy , David Avishai , Eli Elmoalem , Moti Kurnick , Gal Sitton
发明人： Eliezer Weitz , Gil Levy , David Avishai , Eli Elmoalem , Moti Kurnick , Gal Sitton
IPC分类号： H04L12/56
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9073 , H04Q11/0067 , H04Q11/0071
摘要： An enhanced passive optical network (PON) processor adapted to serve a plurality of PON applications is disclosed. The PON processor is a highly integrated communications processor that can operate in different PON modes including, but not limited to, a gigabit PON (GPON), a broadband PON (BPON), an Ethernet PON (EPON), or any combination thereof. In an embodiment of the present invention the provided PON is fabricated on a single integrated circuit (IC).
摘要翻译：公开了一种适用于服务多个PON应用的增强型无源光网络（PON）处理器。 PON处理器是可以在不同PON模式下工作的高度集成的通信处理器，包括但不限于千兆位PON（GPON），宽带PON（BPON），以太网PON（EPON）或其任何组合。在本发明的实施例中，所提供的PON被制造在单个集成电路（IC）上。

7. 发明授权

US08817799B2 Network processor for supporting residential gateway applications 有权
标题翻译：用于支持住宅网关应用的网络处理器
公开(公告)号：US08817799B2
公开(公告)日：2014-08-26
申请号：US13086753
申请日：2011-04-14
申请人： Asaf Koren , Ifat Naaman , Eliezer Weitz , Alex Goldstein , Yariv Aviram
发明人： Asaf Koren , Ifat Naaman , Eliezer Weitz , Alex Goldstein , Yariv Aviram
IPC分类号： H04L12/28
CPC分类号： H04L45/60 , H04L12/2834 , H04L12/2898
摘要： A network processor for performing residential gateway processing tasks. The network processor includes a first cluster of packet processors and a second cluster of packet processors, wherein each of the first cluster and the second cluster includes a main packet processor and a secondary packet processor, wherein the main packet processor performs at least routing of incoming packets and the secondary packet processor performs off-loading tasks for the main packet processor; a plurality of Ethernet media access control (MAC) adapters for interfacing with a plurality of subscriber devices connected to a residential gateway; an external-network MAC adapter for interfacing with a wide area network (WAN) connected to the network processor; and an ingress handler for at least load balancing the processing of packets between the first cluster and the second cluster.
摘要翻译：一种用于执行住宅网关处理任务的网络处理器。网络处理器包括分组处理器的第一簇和分组处理器的第二簇，其中第一簇和第二簇中的每一个包括主分组处理器和辅分组处理器，其中主分组处理器至少执行路由选择分组和次分组处理器执行主分组处理器的卸载任务; 用于与连接到住宅网关的多个订户设备进行接口的多个以太网媒体接入控制（MAC）适配器; 用于与连接到网络处理器的广域网（WAN）进行接口的外部网络MAC适配器; 以及用于至少负载平衡在第一集群和第二集群之间的分组的处理的进入处理器。

8. 发明申请

US20070074218A1 Passive optical network (PON) packet processor 有权
标题翻译：无源光网络（PON）数据包处理器
公开(公告)号：US20070074218A1
公开(公告)日：2007-03-29
申请号：US11349917
申请日：2006-02-09
申请人： Gil Levy , Eliezer Weitz , Eli Elmoalem , Gal Sitton
发明人： Gil Levy , Eliezer Weitz , Eli Elmoalem , Gal Sitton
IPC分类号： G06F9/46
CPC分类号： H04L49/9094 , H04L49/90 , H04L49/9073 , H04Q11/0067 , H04Q11/0071
摘要： A passive optical network (PON) packet processor for processing PON traffic includes a core processor for executing threads related to the processing of PON traffic and a plurality of hardware (HW) accelerators coupled to the core processor for accelerating the processing of said PON traffic. A memory unit is coupled to the core processor for maintaining program and traffic data. In an embodiment of the present invention, the PON packet processor includes a scheduler that optimizes the execution of PON related tasks.
摘要翻译：用于处理PON业务的无源光网络（PON）分组处理器包括用于执行与PON业务处理相关的线程的核心处理器和耦合到核心处理器的多个硬件（HW）加速器，用于加速所述PON业务的处理。存储器单元耦合到核心处理器，用于维护程序和业务数据。在本发明的实施例中，PON分组处理器包括优化PON相关任务的执行的调度器。

9. 发明授权

US5195093A Method and apparatus for ensuring CRC error generation by a data communication station experiencing transmitter exceptions 失效
标题翻译：用于确保经历发射机异常的数据通信站产生CRC错误的方法和装置
公开(公告)号：US5195093A
公开(公告)日：1993-03-16
申请号：US655884
申请日：1991-02-14
申请人： Moshe Tarrab , Yehuda Shaik , Eliezer Weitz
发明人： Moshe Tarrab , Yehuda Shaik , Eliezer Weitz
IPC分类号： G06F11/10 , H04L1/00
CPC分类号： H04L1/0061 , G06F11/10
摘要： A method for ensuring CRC error generation by a data communication station after a transmitter exception such as an underrun whereby a parity bit is preset to a binary one, and toggled in response to successive binary ones of a serial bit stream. Each byte of the serial bit stream is transmitted sequentially. If a transmitter exception occurs, the byte before the exception is transmitted normally. However, only the first seven bits of the last byte are transmitted. The parity bit is sent as an eighth bit of the last byte, ensuring odd parity for the previous bit stream. Thereafter, a byte even parity is sent to assure that the overall message has odd parity. A receiving station interprets two consecutive bytes having the predetermined data pattern as the CRC, thus ensuring that the receiving station will reject the frame.
摘要翻译：一种在诸如欠载的发射机异常之后确保数据通信站产生CRC错误的方法，由此将奇偶校验位预设为二进制位，并且响应于串行比特流的连续的二进制位而被切换。串行比特流的每个字节被顺序地发送。如果发生异常发生，异常发生前的字节正常发送。但是，只发送最后一个字节的前7位。奇偶校验位作为最后一个字节的第八位发送，确保前一个比特流的奇偶校验。此后，发送字节偶校验以确保整个消息具有奇校验。接收站将具有预定数据模式的两个连续字节解释为CRC，从而确保接收站将拒绝该帧。

10. 发明授权

US08451864B2 Passive optical network processor with a programmable data path 有权
标题翻译：无源光网络处理器具有可编程数据路径
公开(公告)号：US08451864B2
公开(公告)日：2013-05-28
申请号：US12821931
申请日：2010-06-23
申请人： Gal Sitton , Asaf Koren , Eliezer Weitz , Ifat Naaman , Igor Ternovsky , Igor Elkanovich
发明人： Gal Sitton , Asaf Koren , Eliezer Weitz , Ifat Naaman , Igor Ternovsky , Igor Elkanovich
IPC分类号： H04J14/00
CPC分类号： H04B10/27 , H04J14/0247 , H04J14/0252 , H04J14/0254 , H04J14/0269 , H04J14/0282 , H04Q11/0067 , H04Q2011/0084
摘要： A passive optical network (PON) processor comprises a packet processor for processing packets belonging to a certain flow through a plurality of processing stages of a programmable data-path; a microprocessor-data for performing one or more user-defined functions in the programmable data-path on designated packets belonging to the certain flow, wherein packets of respective flows to be processed by the microprocessor-data are designated in a flow table; a microprocessor-control for managing connections handled by the PON processor; a data-path bus for connecting the packet processor and the microprocessor-data, wherein the designated packets are transferred between the packet processor and the microprocessor-data on the data-path bus; and a control-path bus for connecting the packet processor and the microprocessor-control.
摘要翻译：无源光网络（PON）处理器包括：分组处理器，用于处理属于通过可编程数据路径的多个处理级的特定流的分组; 用于在属于该特定流的指定分组上的可编程数据路径中执行一个或多个用户定义的功能的微处理器数据，其中由微处理器数据处理的相应流的分组在流表中被指定; 用于管理由PON处理器处理的连接的微处理器控制; 用于连接分组处理器和微处理器数据的数据路径总线，其中指定分组在分组处理器和数据路径总线上的微处理器数据之间传送; 以及用于连接分组处理器和微处理器控制的控制路径总线。

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