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1. 发明授权

US06378064B1 Microcomputer 有权
标题翻译：微电脑
公开(公告)号：US06378064B1
公开(公告)日：2002-04-23
申请号：US09267057
申请日：1999-03-12
申请人： David Alan Edwards , Glenn Ashley Farrall
发明人： David Alan Edwards , Glenn Ashley Farrall
IPC分类号： G06F9305
CPC分类号： G06F11/3648 , G06F11/348
摘要： A computer system comprising a microprocessor on a single integrated circuit chip having an on-chip CPU which includes: a data processing unit for executing instructions; a data link connected between a memory and the data processing unit for passing instructions to the data processing unit; a watch register for storing an instruction comparison code; and a watch comparator coupled to the data link for comparing the instructions passed on the data link with the instruction comparison code and generating a comparison output signal in dependence on the result of the comparison.
摘要翻译：一种计算机系统，包括具有片上CPU的单个集成电路芯片上的微处理器，其包括：用于执行指令的数据处理单元; 连接在存储器和数据处理单元之间的数据链路，用于将指令传递给数据处理单元; 用于存储指令比较码的监视寄存器; 以及观察比较器，其耦合到数据链路，用于将在数据链路上传递的指令与指令比较代码进行比较，并根据比较结果生成比较输出信号。

2. 发明授权

US06591369B1 System and method for communicating with an integrated circuit 有权
公开(公告)号：US06591369B1
公开(公告)日：2003-07-08
申请号：US09410638
申请日：1999-10-01
申请人： David Alan Edwards , Anthony Willis Rich
发明人： David Alan Edwards , Anthony Willis Rich
IPC分类号： G06F1342
CPC分类号： G06F11/3636 , G01R31/31903 , G06F11/3656
摘要： A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

3. 发明授权

US06530047B1 System and method for communicating with an integrated circuit 有权
公开(公告)号：US06530047B1
公开(公告)日：2003-03-04
申请号：US09411815
申请日：1999-10-01
申请人： David Alan Edwards , Stephen James Wright , Bernard Ramanadin
发明人： David Alan Edwards , Stephen James Wright , Bernard Ramanadin
IPC分类号： G01R3128
CPC分类号： G01R31/31903
摘要： A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

4. 发明授权

US06457124B1 Microcomputer having address diversion means for remapping an on-chip device to an external port 有权
标题翻译：具有用于将片上设备重映射到外部端口的地址转移装置的微型计算机
公开(公告)号：US06457124B1
公开(公告)日：2002-09-24
申请号：US09268073
申请日：1999-03-12
申请人： David Alan Edwards , Andrew Michael Jones
发明人： David Alan Edwards , Andrew Michael Jones
IPC分类号： G06F900
CPC分类号： G06F11/3648
摘要： A single integrated circuit chip connected to an external computer device. The chip includes a CPU with registers, a bus for addressing devices assigned to a memory address space of the CPU and providing a parallel path between the CPU and a first memory local to the CPU, an address memory for storing addresses assigned to the devices, and an external port connected to the bus. The port includes an internal parallel signal format connection to the bus and a less parallel external connection to the external computer device. The port forms part of the memory address space of the CPU. The external computer device includes a second memory local to the external computer device and accessible by the CPU through the port. Address diversion means are provided for reconfiguring the memory address space of the CPU to assign to the port memory addresses of another one of the devices.
摘要翻译：连接到外部计算机设备的单个集成电路芯片。芯片包括具有寄存器的CPU，用于寻址分配给CPU的存储器地址空间的设备的总线，并且在CPU和CPU之间的第一存储器之间提供并行路径，用于存储分配给设备的地址的地址存储器，和连接到总线的外部端口。该端口包括与总线的内部并行信号格式连接，并且与外部计算机设备的并行外部连接较少。端口构成CPU的内存地址空间的一部分。外部计算机设备包括本地到外部计算机设备的第二存储器，并且可以由CPU通过端口访问。提供地址转移装置用于重新配置CPU的存储器地址空间以分配给另一个设备的端口存储器地址。

5. 发明申请

US20090138754A1 Memory Errors 有权
标题翻译：内存错误
公开(公告)号：US20090138754A1
公开(公告)日：2009-05-28
申请号：US12323563
申请日：2008-11-26
申请人： David Alan Edwards , Joe Woodward
发明人： David Alan Edwards , Joe Woodward
IPC分类号： G06F11/08 , G06F13/00 , G06F9/00 , H03M13/00 , G11C29/00
CPC分类号： G06F9/4403 , G06F11/1068 , G06F11/1417
摘要： The present invention provides a method of protecting against errors in a boot memory, the method comprising initiating booting of a processor by executing primary boot code from a primary boot memory, and based on the execution of the primary boot code: accessing a data structure comprising a plurality of redundant portions of boot information stored on a secondary boot memory; performing an error check on a plurality of the portions to determine whether those portions contain errors and, based on the error checks, to identify a valid portion; and booting the processor using the valid portion of boot information.
摘要翻译：本发明提供一种防止引导存储器中的错误的方法，所述方法包括：通过从主引导存储器执行主引导代码并基于主引导代码的执行来启动处理器的引导：访问包括存储在次启动存储器上的引导信息的多个冗余部分; 对多个部分执行错误检查以确定这些部分是否包含错误，并且基于错误检查来识别有效部分; 并使用引导信息的有效部分引导处理器。

6. 发明授权

US06918065B1 Method for compressing and decompressing trace information 失效
标题翻译：压缩和解压缩跟踪信息的方法
公开(公告)号：US06918065B1
公开(公告)日：2005-07-12
申请号：US09411794
申请日：1999-10-01
申请人： David Alan Edwards , Anthony Willis Rich
发明人： David Alan Edwards , Anthony Willis Rich
IPC分类号： G06F11/28 , G06F11/00 , G06F11/34
CPC分类号： G06F11/348
摘要： A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.
摘要翻译：提供用于执行非侵入性跟踪的系统，其从一个或多个处理器接收跟踪信息。跟踪系统可以由用户配置为以各种模式操作以灵活地存储或发送跟踪信息。跟踪系统包括一个内存映射的FIFO，可以在不影响处理器性能的情况下被访问。在一个方面，跟踪系统包括跟踪缓冲器，其以处理器的内部时钟速度接收跟踪信息。在另一个实施例中，提供了压缩协议，用于在将消息发送到外部系统之前或在存储器中存储消息的情况下在片上缓存跟踪消息。

7. 发明授权

US06684348B1 Circuit for processing trace information 失效
标题翻译：追踪信息处理电路
公开(公告)号：US06684348B1
公开(公告)日：2004-01-27
申请号：US09409612
申请日：1999-10-01
申请人： David Alan Edwards , Anthony Willis Rich
发明人： David Alan Edwards , Anthony Willis Rich
IPC分类号： B06F1100
CPC分类号： G06F11/3636 , G06F11/3648
摘要： A system for performing non-intrusive trace is provided which receives trace information from one or more processors. The trace system may be configured by a user to operate in various modes for flexibly storing or transmitting the trace information. The trace system includes a FIFO which is memory-mapped and is capable of being accessed without affecting processor performance. In one aspect, the trace system includes a trace buffer which receives trace information at an internal clock speed of the processor. In another embodiment, a compression protocol is provided for compressing trace messages on-chip prior to transmitting the messages to an external system or storing the messages in memory.
摘要翻译：提供用于执行非侵入性跟踪的系统，其从一个或多个处理器接收跟踪信息。跟踪系统可以由用户配置为以各种模式操作以灵活地存储或发送跟踪信息。跟踪系统包括一个内存映射的FIFO，可以在不影响处理器性能的情况下被访问。在一个方面，跟踪系统包括跟踪缓冲器，其以处理器的内部时钟速度接收跟踪信息。在另一个实施例中，提供了压缩协议，用于在将消息发送到外部系统之前或在存储器中存储消息的情况下在片上缓存跟踪消息。

8. 发明授权

US06567932B2 System and method for communicating with an integrated circuit 有权
公开(公告)号：US06567932B2
公开(公告)日：2003-05-20
申请号：US09411795
申请日：1999-10-01
申请人： David Alan Edwards , Anthony Willis Rich
发明人： David Alan Edwards , Anthony Willis Rich
IPC分类号： G06F1100
CPC分类号： G06F11/364 , G06F11/25 , G06F11/267 , G06F11/3656
摘要： A system and method for communicating with an integrated circuit is provided that allows an integrated circuit to communicate debugging information and system bus transaction information with an external system. The system may include an interface protocol that provides flow control between the integrated circuit and the external system. The system may include a high-speed link and/or a JTAG link for communicating information. A link may be automatically selected by a debug circuit, or selected by an on-chip device or external system. The high-speed link enables real-time collection of trace information. Links may be memory-mapped, such that on-chip devices and other devices attached to the system bus may access the external system. The high-speed link may also operate at a rate which is integrally coupled with a rate of the processor or system bus. Further, the high-speed link may be adapted to change speeds in response to a change in operating speed of the system bus or processor. The JTAG interface may utilize standard JTAG components and instructions such that external devices such as debug adaptors adopting these components and instructions may be re-used for different integrated circuit types. Information transmitted over the JTAG or high-speed link may be compressed to optimize available bandwidth of the links. Also, processor control signals can be transferred through links that allow an external system to manipulate and monitor operation of the processor and its associated modules.

9. 发明授权

US06301657B1 System and method for booting a computer 有权
标题翻译：用于引导计算机的系统和方法
公开(公告)号：US06301657B1
公开(公告)日：2001-10-09
申请号：US09621644
申请日：2000-07-21
申请人： Andrew Michael Jones , David Alan Edwards , Michael David May
发明人： Andrew Michael Jones , David Alan Edwards , Michael David May
IPC分类号： G06F944
CPC分类号： G06F11/3656 , G06F9/4401 , G06F11/1417
摘要： There is disclosed a computer,system including a microprocessor on an integrated circuit chip comprising an on-chip CPU and a communication bus. The communication bus provides a parallel communication path between the CPU and the first memory local to the CPU. An external port of the integrated circuit is connected to said bus and to an external computer device having a second memory. The external computer device is operable to transmit control signals through the port: a) to suspend execution by the CPU of instructions obtained from the first memory; b) to provide from the second memory boot code to be executed by the CPU; and c) to restart operation of the CPU using said boot code. There is also disclosed a method of operating such a computer system.
摘要翻译：公开了一种包括在包括片上CPU和通信总线的集成电路芯片上的微处理器的计算机系统。通信总线在CPU和本地CPU的第一个存储器之间提供并行通信路径。集成电路的外部端口连接到所述总线和具有第二存储器的外部计算机设备。外部计算机设备可操作以通过端口传输控制信号：a）暂停由CPU执行从第一存储器获得的指令; b）提供由CPU执行的第二存储器引导代码; 以及c）使用所述引导代码重新启动CPU的操作。还公开了一种操作这种计算机系统的方法。

10. 发明授权

US08479039B2 Memory errors 有权
标题翻译：内存错误
公开(公告)号：US08479039B2
公开(公告)日：2013-07-02
申请号：US13187061
申请日：2011-07-20
申请人： David Alan Edwards , Joe Woodward
发明人： David Alan Edwards , Joe Woodward
IPC分类号： G06F11/00
CPC分类号： G06F9/4403 , G06F11/1068 , G06F11/1417
摘要： The present invention provides a method of protecting against errors in a boot memory, the method comprising initiating booting of a processor by executing primary boot code from a primary boot memory, and based on the execution of the primary boot code: accessing a data structure comprising a plurality of redundant portions of boot information stored on a secondary boot memory; performing an error check on a plurality of the portions to determine whether those portions contain errors and, based on the error checks, to identify a valid portion; and booting the processor using the valid portion of boot information.
摘要翻译：本发明提供一种防止引导存储器中的错误的方法，所述方法包括：通过从主引导存储器执行主引导代码并基于主引导代码的执行来启动处理器的引导：访问包括存储在次启动存储器上的引导信息的多个冗余部分; 对多个部分执行错误检查以确定这些部分是否包含错误，并且基于错误检查来识别有效部分; 并使用引导信息的有效部分引导处理器。

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