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1. 发明授权

US5142631A System for queuing individual read or write mask and generating respective composite mask for controlling access to general purpose register 失效
标题翻译：系统用于单独读取或写入掩模和生成用于控制访问一般目的寄存器的相关复合掩码
公开(公告)号：US5142631A
公开(公告)日：1992-08-25
申请号：US306773
申请日：1989-02-03
申请人： John E. Murray , Mark A. Firstenberg , David B. Fite , Michael M. McKeon , Wiliam R. Grundmann , David A. Webb, Jr. , Ronald M. Salett , Tryggve Fossum , Dwight P. Manley , Ricky C. Hetherington
发明人： John E. Murray , Mark A. Firstenberg , David B. Fite , Michael M. McKeon , Wiliam R. Grundmann , David A. Webb, Jr. , Ronald M. Salett , Tryggve Fossum , Dwight P. Manley , Ricky C. Hetherington
IPC分类号： G06F9/38
CPC分类号： G06F9/355 , G06F9/345 , G06F9/3836 , G06F9/3838 , G06F9/3857
摘要： A method is provided for preprocessing multiple instructions prior to execution of such instructions in a digital computer having an instruction decoder, an instruction execution unit, and multiple general purpose registers which are read to produce memory addresses during the preprocessing. The method comprises: (1) avoiding the preprocessing of a current instruction to read a general purpose register to produce a memory address prior to the modification of the contents of that register by a preceding instruction by (a) generating a composite write mask having a bit set for each general purpose register whose contents are to be modified by at least one of a plurality of decoded by not-yet-executed instructions preceding the current instruction, and (b) stalling the preprocessing of the current instruction when a general purpose register to be read by the current instruction is a register having a bit set in the write mask, and/or (2) avoiding the preprocessing of a current instruction which modifies the contents of a general purpose register that is to be read by a preceding instruction by (a) generating a composite read mask having a bit set for each general purpose register to be read by at least one of a plurality of decoded but not-yet-executed instructions preceding the current instruction, and (b) stalling the preprocessing of the current instruction when a general purpose register whose contents are to be modified by the current instruction is a register having a bit set in the read mask.

2. 发明授权

US5349651A System for translation of virtual to physical addresses by operating memory management processor for calculating location of physical address in memory concurrently with cache comparing virtual addresses for translation 失效
标题翻译：用于通过操作存储器管理处理器来计算虚拟地址到物理地址的系统，用于计算存储器中的物理地址的位置并与高速缓存比较虚拟地址进行翻译
公开(公告)号：US5349651A
公开(公告)日：1994-09-20
申请号：US746007
申请日：1991-08-09
申请人： Ricky C. Hetherington , David A. Webb, Jr. , David B. Fite , John E. Murray , Tryggve Fossum , Dwight P. Manley
发明人： Ricky C. Hetherington , David A. Webb, Jr. , David B. Fite , John E. Murray , Tryggve Fossum , Dwight P. Manley
IPC分类号： G06F12/08 , G06F12/10 , G06F12/00
CPC分类号： G06F12/0855 , G06F12/1045
摘要： In the field of high speed computers it is common for a central processing unit to reference memory locations via a virtual addressing scheme, rather than by the actual physical memory addresses. In a multi-tasking environment, this virtual addressing scheme reduces the possibility of different programs accessing the same physical memory location. Thus, to maintain computer processing speed, a high speed translation buffer cache is employed to perform the necessary virtual-to-physical conversions for memory reference instructions. The translation buffer cache stores a number of previously translated virtual addresses and their corresponding physical addresses. A memory management processor is employed to update the translation buffer cache with the most recently accessed physical memory locations. The memory management processor consists of a state machine controlling hardware specifically designed for the purpose of updating the translation buffer cache. The memory management processor calculates an address of a location in the memory where the physical address is stored concurrently with the translation buffer cache comparing the virtual address with already stored virtual addresses. With this arrangement the memory management unit can immediately access memory to retrieve the physical address upon a "miss" by the translation buffer cache.
摘要翻译：在高速计算机领域，中央处理单元通常通过虚拟寻址方案而不是实际物理存储器地址来引用存储器位置。在多任务环境中，这种虚拟寻址方案减少了访问相同物理内存位置的不同程序的可能性。因此，为了维持计算机处理速度，使用高速转换缓冲器缓存来对存储器参考指令执行必要的虚拟到物理转换。翻译缓冲区高速缓存存储多个先前转换的虚拟地址及其对应的物理地址。使用存储器管理处理器来更新具有最近访问的物理存储器位置的翻译缓冲器高速缓存。存储器管理处理器由控制硬件的状态机组成，其特别设计用于更新翻译缓冲器高速缓存。存储器管理处理器计算存储器中与物理地址同时存储的位置的地址，该地址与翻译缓冲器高速缓存将虚拟地址与已存储的虚拟地址进行比较。利用这种安排，存储器管理单元可以立即访问存储器，以在翻译缓冲器高速缓存器“遗漏”时检索物理地址。

3. 发明授权

US5222223A Method and apparatus for ordering and queueing multiple memory requests 失效
标题翻译：用于订购和排队多种内存请求的方法和装置
公开(公告)号：US5222223A
公开(公告)日：1993-06-22
申请号：US306870
申请日：1989-02-03
申请人： David A. Webb, Jr. , Ricky C. Hetherington , John E. Murray , Tryggve Fossum , Dwight P. Manley
发明人： David A. Webb, Jr. , Ricky C. Hetherington , John E. Murray , Tryggve Fossum , Dwight P. Manley
IPC分类号： G06F12/08 , G06F9/38 , G06F12/00 , G06F12/10 , G06F13/18
CPC分类号： G06F13/18 , G06F12/1054 , G06F9/3824
摘要： In a pipelined computer system 10, memory access functions (requests) are simultaneously generated from a plurality of different locations. These multiple requests are passed through a multiplexer 50 according to a prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. In this manner, the complex task of converting virtual-to-physical addresses is accomplished for all memory access requests by a single translation buffer 30. The physical address output from the translation buffer 30 are passed to a cache 28 through a second multiplexer 40 according to a second prioritization scheme based upon the operational proximity of the request to the instruction currently being executed. The first and second prioritization schemes differ, in that the memory is capable of handling other requests while a higher priority "miss" is pending. Thus, the prioritization scheme temporarily suspends the higher priority request while the desired data is being retrieved from main memory 14, but continues to operate on a lower priority request so that the overall operation will be enhanced if the lower priority request hits in the cache 28.

4. 发明授权

US4985825A System for delaying processing of memory access exceptions until the execution stage of an instruction pipeline of a virtual memory system based digital computer 失效
标题翻译：用于延迟存储器访问异常的处理的系统，直到基于虚拟存储器系统的数字计算机的指令流水线的执行阶段为止
公开(公告)号：US4985825A
公开(公告)日：1991-01-15
申请号：US306866
申请日：1989-02-03
申请人： David A. Webb, Jr. , David B. Fite , Ricky C. Hetherington , Francis X. McKeen , Mark A. Firstenberg , John E. Murray , Dwight P. Manley , Ronald M. Salett , Tryggve Fossum
发明人： David A. Webb, Jr. , David B. Fite , Ricky C. Hetherington , Francis X. McKeen , Mark A. Firstenberg , John E. Murray , Dwight P. Manley , Ronald M. Salett , Tryggve Fossum
IPC分类号： G06F9/38 , G06F11/07 , G06F12/08 , G06F12/10
CPC分类号： G06F9/3865 , G06F11/073 , G06F11/0772 , G06F12/1045
摘要： A technique for processing memory access exceptions along with pre-fetched instructions in a pipelined instruction processing computer system is based upon the concept of pipelining exception information along with other parts of the instruction being executed. In response to the detection of access exceptions at a pipeline stage, corresponding fault information is generated and transferred along the pipeline. The fault information is acted upon only when the instruction reaches the execution stage of the pipeline. Each stage of the instruction pipeline is ported into the front end of a memory unit adapted to perform the virtual-to-physical address translation; each port being provided with storage for virtual addresses accompanying an instruction as well as storage for corresponding fault information. When a memory access exception is encountered at the front end of the memory unit, the fault information generated therefrom is loaded into the storage and the port is prevented from accepting further references.

5. 发明授权

US4888679A Method and apparatus using a cache and main memory for both vector processing and scalar processing by prefetching cache blocks including vector data elements 失效
标题翻译：使用高速缓存和主存储器的方法和装置，用于通过预取包括向量数据元素的高速缓存块来进行矢量处理和标量处理
公开(公告)号：US4888679A
公开(公告)日：1989-12-19
申请号：US142794
申请日：1988-01-11
申请人： Tryggve Fossum , Ricky C. Hetherington , David B. Fite, Jr. , Dwight P. Manley , Francis X. McKeen , John E. Murray
发明人： Tryggve Fossum , Ricky C. Hetherington , David B. Fite, Jr. , Dwight P. Manley , Francis X. McKeen , John E. Murray
IPC分类号： G06F12/06 , G06F9/38 , G06F12/02 , G06F12/08 , G06F15/78 , G06F17/16
CPC分类号： G06F15/8069 , G06F12/0207 , G06F12/0855 , G06F9/3455 , G06F9/383
摘要： A main memory and cache suitable for scalar processing are used in connection with a vector processor by issuing prefetch requests in response to the recognition of a vector load instruction. A respective prefetch request is issued for each block containing an element of the vector to be loaded from memory. In response to a prefetch request, the cache is checked for a "miss" and if the cache does not include the required block, a refill request is sent to the main memory. The main memory is configured into a plurality of banks and has a capability of processing multiple references. Therefore the different banks can be referenced simultaneously to prefetch multiple blocks of vector data. Preferably a cache bypass is provided to transmit data directly to the vector processor as the data from the main memory are being stored in the cache. In a preferred embodiment, a vector processor is added to a digital computing system including a scalar processor, a virtual address translation buffer, a main memory and a cache. The scalar processor includes a microcode interpreter which sends a vector load command to the vector processing unit and which also generates vector prefetch requests. The addresses for the data blocks to be prefetched are computed based upon the vector address, the length of the vector and the "stride" or spacing between the addresses of the elements of the vector.
摘要翻译：适用于标量处理的主存储器和缓存器与矢量处理器结合使用以响应于矢量加载指令的识别发出预取请求。为包含要从存储器加载的向量的元素的每个块发出相应的预取请求。响应于预取请求，检查缓存是否存在“未命中”，并且如果高速缓存不包括所需的块，则向主存储器发送补充请求。主存储器被配置成多个存储体并且具有处理多个引用的能力。因此，可以同时引用不同的库来预取多个向量数据块。优选地，提供高速缓存旁路以将数据直接发送到向量处理器，因为来自主存储器的数据正被存储在高速缓存中。在优选实施例中，将向量处理器添加到包括标量处理器，虚拟地址转换缓冲器，主存储器和高速缓存的数字计算系统。标量处理器包括微代码解释器，其向向量处理单元发送向量加载命令，并且还生成向量预取请求。要预取的数据块的地址是基于向量地址，向量的长度和向量元素的地址之间的“stride”或间距来计算的。

6. 发明授权

US4995041A Write back buffer with error correcting capabilities 失效
标题翻译：回写具有纠错功能的缓冲区
公开(公告)号：US4995041A
公开(公告)日：1991-02-19
申请号：US306703
申请日：1989-02-03
申请人： Ricky C. Hetherington , Tryggve Fossum , Maurice B. Steinman , David A. Webb, Jr.
发明人： Ricky C. Hetherington , Tryggve Fossum , Maurice B. Steinman , David A. Webb, Jr.
IPC分类号： G06F11/10 , G06F12/08 , G06F12/16
CPC分类号： G06F11/1048 , G06F11/1064 , G06F12/0804
摘要： In the operation of high-speed computers, it is frequently advantageous to employ a high speed cache memory within each CPU of a multiple CPU computer system. A standard, slower memory configuration remains in use for the large, common main memory, but those portions of main memory which are expected to be used heavily are copied into the cache memory. Thus, on many memory references, the faster cache memory is exploited, while only infrequent references to the slower main memory are necessary. This configuration generally speeds the overall operation of the computer system; however, memory integrity problems arise by maintaining two separate copies of selected portions of main memory. Accordingly, the memory access unit of the CPU uses error correction code (ECC) hardware to ensure the integrity of the data delivered between the cache and main memory. The prevent the ECC hardware from slowing the overall operation of the CPU, the error correction is performed underneath a write back operation. Data contained in the cache, which will be displaced by data received from main memory 10, is transferred to a write back buffer (WBB) during that period of time between the request for data from the main memory and actual delivery of the requested data. Further, the ECC hardware also operates on the cache data being written to the WBB. Accordingly, a performance penalty is avoided by performing error correction and preremoving the cache data during that idle period of time.

7. 发明授权

US5019965A Method and apparatus for increasing the data storage rate of a computer system having a predefined data path width 失效
标题翻译：用于增加具有预定数据路径宽度的计算机系统的数据存储速率的方法和装置
公开(公告)号：US5019965A
公开(公告)日：1991-05-28
申请号：US306826
申请日：1989-02-03
申请人： David A. Webb, Jr. , Ricky C. Hetherington , Ronald M. Salett , Trvggve Fossum , Dwight P. Manley
发明人： David A. Webb, Jr. , Ricky C. Hetherington , Ronald M. Salett , Trvggve Fossum , Dwight P. Manley
IPC分类号： G06F12/08 , G06F13/40
CPC分类号： G06F12/0886 , G06F13/4018
摘要： In a computer system, the flow of data from the execution unit to the cache 28 is enhanced by pairing individual, sequential longword write operations into a simultaneous quadword write operation. Primary and secondary writebuffers 50, 52 sequentially receive the individual longwords during first and second clock cycles and simultaneously present the individual longwords over a quadword wide bus to the cache 28. During the first clock cycle, when the cache 28 is not performing the quadword write operation, the cache 28 is free to perform the requisite lookup routine on the address of the first longword of data to determine if the quadword of address space is available in the cache. Thus, the flow of data to the cache 28 is maximized.

8. 发明授权

US4982402A Method and apparatus for detecting and correcting errors in a pipelined computer system 失效
标题翻译：用于检测和纠正流水线计算机系统中的错误的方法和装置
公开(公告)号：US4982402A
公开(公告)日：1991-01-01
申请号：US306828
申请日：1989-02-03
申请人： Richard C. Beaven , Michael B. Evans , Tryggve Fossum , Ricky C. Hetherington , William R. Grundmann , John E. Murray , Ronald M. Salett
发明人： Richard C. Beaven , Michael B. Evans , Tryggve Fossum , Ricky C. Hetherington , William R. Grundmann , John E. Murray , Ronald M. Salett
IPC分类号： G06F9/38 , G06F11/07 , G06F11/14 , G06F11/267 , G06F15/16 , G06F15/177
CPC分类号： G06F11/2236 , G06F11/0724 , G06F11/0772 , G06F11/0781 , G06F11/1405 , G06F9/3863
摘要： In a multiprocessor system, an error occurring in any one of the CPUs may have an impact upon the operation of the remaining CPUs, and therefore these errors must be handled quickly. The errors are grouped into two categories: synchronous errors (those that must be corrected immediately to allow continued processing of the current instruction); and asynchronous errors (those errors that do not affect execution of the current instruction and may be handled upon completing execution of the current instruction). Since synchronous errors prevent continued execution of the current instruction, it is preferable that the last stable state conditions of the faulting CPU be restored and the faulting instruction reexecuted. These stable state conditions advantageously occur between the execution of each instruction. However, in a pipelined computer system, it is difficult to identify the beginning and ending of a selected instruction since multiple instructions are in process at the same time. Accordingly, the execution unit is selected to be the point of synchronization between error handling and instruction execution. Once the error is indentified as asynchronous or synchronous and the execution unit allows the instruction to complete or rolls back the state conditions to their preinstruction values, error analyzing software examines the condition of the suspect data latches in the CPU. A serial diagnostic link stops the system clock of the CPU and serially loads the CPU data latches into the System Processor Unit for error determination. Thereafter, the CPU system clock is restarted and the CPU resumes execution.

9. 发明授权

US5125083A Method and apparatus for resolving a variable number of potential memory access conflicts in a pipelined computer system 失效
标题翻译：用于解决管道计算机系统中可变存储器访问冲突的可变数量的方法和装置
公开(公告)号：US5125083A
公开(公告)日：1992-06-23
申请号：US306767
申请日：1989-02-03
申请人： David B. Fite , Tryggve Fossum , Ricky C. Hetherington , John E. Murray , Jr. David A. Webb
发明人： David B. Fite , Tryggve Fossum , Ricky C. Hetherington , John E. Murray , Jr. David A. Webb
IPC分类号： G06F9/38
CPC分类号： G06F9/3816 , G06F9/383 , G06F9/3834
摘要： An operand processing unit delivers a specified address and at least one read/write signal in response to an instruction being a source of destination operand, and delivers the source operand to an execution unit in response to completion of the preprocessing. The execution unit receives the source operand, executes it and delivers the resultant data to memory. A "write queue" receives the write addresses of the destination operands from the operand processing unit, stores the write addresses, and delivers the stored preselected addresses to memory in response to receiving the resultant data corresponding to the preselected address. The addresses of the source operand is compared to the write addresses stored in the write queue, and the operand processing unit is stalled whenever at least one of the write addresses in the write queue is equivalent to the read address. Therefore, fetching of the operand is delayed until the corresponding resultant data has been delivered by the execution unit.

10. 发明授权

US5113515A Virtual instruction cache system using length responsive decoded instruction shifting and merging with prefetch buffer outputs to fill instruction buffer 失效
标题翻译：虚拟指令高速缓存系统使用长度响应的指令转换和与预置缓冲区输出的合并来填充指令缓冲区
公开(公告)号：US5113515A
公开(公告)日：1992-05-12
申请号：US306831
申请日：1989-02-03
申请人： David B. Fite , Ricky C. Hetherington , Michael M. McKeon , Dwight P. Manley , John E. Murray
发明人： David B. Fite , Ricky C. Hetherington , Michael M. McKeon , Dwight P. Manley , John E. Murray
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30145 , G06F9/30149 , G06F9/3816
摘要： An instruction buffer of a high speed digital computer controls the flow of instruction stream to an instruction decoder. The buffer provides the decoder with nine bytes of sequential instruction stream. The instruction set used by the computer is of the variable length type, such that the decoder consumes a variable number of the instruction stream bytes, depending upon the type of instruction being decoded. As each instruction is consumed, a shifter removes the consumed bytes and repositions the remaining bytes into the lowest order positions. The byte positions left empty by the shifter are filled by instruction stream retrieved from one of a pair of prefetch buffers (IBEX, IBEX2) or from a virtual instruction cache. These prefetch buffers are arranged to hold the next two subsequent quadwords of instruction stream and provide the desired missing bytes. The IBEX prefetch buffer is filled from the instruction cache after being emptied, but prior to those particular bytes being requested to fill the instruction decoder. This two level prefetching allows the relatively slow process of cache access to be performed during noncritical time. The instruction decoder is not stalled, waiting for a cache refill, but can ordinarily obtain the desired bytes of instruction stream from the prefetch buffer.

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