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1. 发明授权

US06667650B2 Current leakage compensation circuit and method 有权
标题翻译：电流泄漏补偿电路及方法
公开(公告)号：US06667650B2
公开(公告)日：2003-12-23
申请号：US10266885
申请日：2002-10-08
申请人： David A. Gammie , Jeffrey B. Parfenchuck , David M. Jones , Jerry L. Doorenbos
发明人： David A. Gammie , Jeffrey B. Parfenchuck , David M. Jones , Jerry L. Doorenbos
IPC分类号： G06G712
CPC分类号： H03F1/302
摘要： A leakage compensation circuit and technique is provided that compensates for losses in a referenced current of an amplifier circuit due to leakage elements. The leakage compensation circuit is configured to inject current substantially equal in magnitude to the leakage current into one or more junctions of the amplifier circuit to compensate for lost referenced current due to leakage. As a result, the amplifier circuit and various devices can realize the flow of the reference current as substantially intended without detrimental effects of leakage current, thus maintaining the integrity of the referenced current. The leakage compensation circuit comprises an array of compensation regions configured to approximate the collective loss that is created by the leakage elements and provide a compensation current substantially equal in magnitude to one or more junctions to compensate for lost referenced current.
摘要翻译：提供一种泄漏补偿电路和技术，其补偿由于泄漏元件引起的放大器电路的参考电流中的损耗。泄漏补偿电路被配置为将大小相等于泄漏电流的电流注入放大器电路的一个或多个结，以补偿由于泄漏引起的丢失的参考电流。结果，放大器电路和各种器件可以实现基本上预期的参考电流的流动，而不会有泄漏电流的有害影响，从而保持参考电流的完整性。泄漏补偿电路包括补偿区域的阵列，其被配置为近似由泄漏元件产生的共同损耗，并提供与一个或多个结点基本相等的补偿电流，以补偿丢失的参考电流。

2. 发明授权

US06801075B2 Method and circuit for base current compensation 有权
标题翻译：基极电流补偿方法及电路
公开(公告)号：US06801075B2
公开(公告)日：2004-10-05
申请号：US10263262
申请日：2002-10-02
申请人： David A. Gammie , Jeffery B. Parfenchuck , Jerry L. Doorenbos
发明人： David A. Gammie , Jeffery B. Parfenchuck , Jerry L. Doorenbos
IPC分类号： G06G714
CPC分类号： G05F3/265
摘要： A base current compensation circuit is configured for injecting base current to the base of a transistor device to compensate for the lost current demanded by a transistor base. The base current compensation circuit is configured to inject current into the base of the transistor without the headroom requirements, as well as being less complex than other approaches. An exemplary base current compensation circuit comprises a sampling circuit and a current mirror feedback circuit configured for providing multiples of the base current demanded by the transistor device.
摘要翻译：基极电流补偿电路被配置为将基极电流注入到晶体管器件的基极以补偿晶体管基极所需的损耗电流。基极电流补偿电路被配置为将电流注入晶体管的基极，而没有余量要求，并且不如其他方法复杂。示例性基极电流补偿电路包括采样电路和被配置为提供晶体管器件所要求的基极电流倍数的电流镜反馈电路。

3. 发明授权

US06844775B2 Operational amplifier with adjustable input offset 有权
标题翻译：具有可调输入偏移的运算放大器
公开(公告)号：US06844775B2
公开(公告)日：2005-01-18
申请号：US10431793
申请日：2003-05-07
申请人： Jerry L. Doorenbos , David M. Jones , Mikhail V. Ivanov
发明人： Jerry L. Doorenbos , David M. Jones , Mikhail V. Ivanov
IPC分类号： H03F3/45 , H03F1/02
CPC分类号： H03F3/45986 , H03F2200/261 , H03F2203/45101
摘要： An operational amplifier having an adjustable input offset is provided that can improve dynamic performance by allowing processing of the input signal in continuous-time. The amplifier circuit comprises an input source and an operational amplifier configured with an adjustable input offset circuit. The adjustable input offset circuit enables cancellation of the offset error from any input sources prior to being translated or gained up by the operational amplifier, thus improving the dynamic range of the operational amplifier. The adjustable input offset circuit can be configured within a signal path of an auto-zero loop of the operational amplifier, or with a continuous-time implementation.
摘要翻译：提供了具有可调输入偏移的运算放大器，其可以通过允许连续地处理输入信号来改善动态性能。放大器电路包括输入源和配置有可调输入偏移电路的运算放大器。可调输入偏移电路能够在由运算放大器转换或增益之前消除任何输入源的偏移误差，从而改善运算放大器的动态范围。可调输入偏移电路可以配置在运算放大器的自动调零回路的信号路径中，或者连续执行。

4. 发明授权

US06255807B1 Bandgap reference curvature compensation circuit 有权
标题翻译：带隙参考曲率补偿电路
公开(公告)号：US06255807B1
公开(公告)日：2001-07-03
申请号：US09691638
申请日：2000-10-18
申请人： Jerry L. Doorenbos , David M. Jones
发明人： Jerry L. Doorenbos , David M. Jones
IPC分类号： G05F316
CPC分类号： G05F3/30 , Y10S323/907
摘要： A temperature curvature compensation technique and circuit can be realized through the generation of a temperature curvature compensation voltage provided by measuring the difference between the base-emitter voltage Vbe of two different transistors operating at two different temperature coefficient quiescent currents. This voltage difference measured between two such transistors results in a scaled voltage that is representative of the temperature curvature of the base-emitter voltage Vbe of a transistor, and which can then be summed to the bandgap reference output to provide a temperature compensated, bandgap reference voltage. The above method can be carried out in an amplifier circuit configured to receive and sum the temperature curvature compensation voltage and the bandgap reference output voltage into the temperature compensated, bandgap reference voltage. In addition, the summing of the temperature curvature compensation voltage and the bandgap reference output voltage may be realized through the application of a dual differential pair amplifier configuration which operates as a gm source. Further, scaling of the respective input voltages for each differential pair can be provided by the amplifier circuit. Moreover, the dual differential pair amplifier may be incorporated into a buffer amplifier configuration to receive a bandgap reference voltage and provide a buffered output or, integrated with a bandgap reference circuit directly into an amplifier circuit.
摘要翻译：温度曲率补偿技术和电路可以通过产生通过测量以两种不同温度系数静态电流工作的两个不同晶体管的基极 - 发射极间电压Vbe之间的差提供的温度曲率补偿电压来实现。在两个这样的晶体管之间测量的这个电压差导致代表晶体管的基极 - 发射极电压Vbe的温度曲率的缩放电压，然后可以将其相加到带隙基准输出以提供温度补偿的带隙基准电压。上述方法可以在放大器电路中进行，该放大器电路被配置为将温度曲率补偿电压和带隙参考输出电压接收并加到温度补偿带隙参考电压中。此外，温度曲率补偿电压和带隙参考输出电压的相加可以通过应用作为gm源工作的双差分对放大器配置来实现。此外，放大电路可以提供每个差分对的各个输入电压的缩放。此外，双差分对放大器可以并入缓冲放大器配置中以接收带隙参考电压并提供缓冲输出，或者与带隙参考电路集成到放大器电路中。

5. 发明授权

US08806083B2 Identification address configuration circuit and method without use of dedicated address pins 有权
标题翻译：识别地址配置电路和方法，不使用专用地址引脚
公开(公告)号：US08806083B2
公开(公告)日：2014-08-12
申请号：US11803465
申请日：2007-05-15
申请人： Jerry L. Doorenbos
发明人： Jerry L. Doorenbos
IPC分类号： G06F3/00 , G06F13/38
CPC分类号： G06F13/385 , G06F13/4291
摘要： An identification address of a sensor interface device is configured in response to the order of connection of first (DXP1) and second (DXN1) package pins to electrodes of a sensor (Q0). A sensor signal processing circuit (23) has first and second inputs coupled through the first and second pins to the sensor for converting a parameter sensed by the sensor to a different representation. A current is forced through the first pin to produce either a high or low voltage on the first pin depending on the order of connection of the first and second pins to the electrodes of the sensor. A voltage on the first pin is compared with a reference voltage to produce a comparison signal which is mapped to produce the identification address.
摘要翻译：响应于第一（DXP1）和第二（DXN1）封装引脚到传感器（Q0）的电极的连接顺序来配置传感器接口装置的识别地址。传感器信号处理电路（23）具有通过第一和第二引脚耦合到传感器的第一和第二输入，用于将由传感器感测的参数转换成不同的表示。根据第一和第二引脚与传感器的电极的连接顺序，迫使电流通过第一引脚产生第一引脚上的高电压或低电压。将第一引脚上的电压与参考电压进行比较，以产生映射以产生识别地址的比较信号。

6. 发明申请

US20080258959A1 Integrating/SAR ADC and method with low integrator swing and low complexity 有权
标题翻译：集成/ SAR ADC和低积分摆幅和低复杂度的方法
公开(公告)号：US20080258959A1
公开(公告)日：2008-10-23
申请号：US12072968
申请日：2008-02-29
申请人： Dimitar T. Trifonov , Jerry L. Doorenbos
发明人： Dimitar T. Trifonov , Jerry L. Doorenbos
IPC分类号： H03M1/12
CPC分类号： H03M1/145 , H03M1/46 , H03M3/46
摘要： A reconfigurable circuit (10) includes an integrator (30) having switches (SW1-6) for selectively coupling input capacitors (C0,1,2,3,6,7) and integrating capacitors (C4,5) to terminals of the integrator (30) for operation of a hybrid delta-sigma/SAR ADC (400) so as to create a reference voltage value (Vref) equal to the sum of a first voltage (ΔVbe) and a second voltage (Vbe). A first integration is performed to reduce the integrator output voltage swing. A residue (Vresidue) of the integrator is multiplied by 2. Then the second voltage (Vbe) is integrated in a first direction if a comparator (22) coupled to the integrator changes state or in an opposite direction if the comparator does not change state. The first voltage (ΔVbe) is integrated in a direction that causes the integrator output voltage (Vout) to equal either 2×Vresidue−Vref or 2×Vresidue+Vref.
摘要翻译：可重新配置电路（10）包括具有用于选择性地将输入电容器（C 0,1,2,3,6,7）和积分电容器（C 4,5）耦合到端子的开关（SW1-6）的积分器（30）用于操作混合Δ-Σ/ SAR ADC（400）的积分器（30），以便产生等于第一电压（DeltaVbe）和第二电压（Vbe）之和的参考电压值（Vref）。执行第一次积分以减小积分器输出电压摆幅。如果比较器（22）耦合到积分器，则如果比较器不改变状态，则将第二电压（Vbe）积分在第一方向上。如果比较器（22）耦合到积分器，则将积分器的残差（Vresidue）乘以2.然后，。第一电压（DeltaVbe）集成在使积分器输出电压（Vout）等于2xVresidue-Vref或2xVresidue + Vref的方向上。

7. 发明申请

US20080258951A1 Hybrid Delta-Sigma/SAR Analog to Digital Converter and Methods for Using Such 有权
标题翻译：混合Delta-Sigma / SAR模数转换器及其使用方法
公开(公告)号：US20080258951A1
公开(公告)日：2008-10-23
申请号：US11738566
申请日：2007-04-23
申请人： Jerry L. Doorenbos , Marco A. Gardner , Dimitar T. Trifonov
发明人： Jerry L. Doorenbos , Marco A. Gardner , Dimitar T. Trifonov
IPC分类号： H03M3/00
CPC分类号： H03M1/145 , H03M1/46 , H03M3/43 , H03M3/456 , H03M3/46
摘要： Various systems and methods for capturing data are disclosed. For example, some embodiments of the present invention provide methods for performing a first analog to digital conversion using a delta-sigma based analog to digital converter, and performing a second analog to digital conversion using a SAR based analog to digital converter. The delta-sigma converter provides a first portion of a conversion result, and the SAR based analog to digital converter provides a second portion of the conversion result. The methods further include combining the first portion of the conversion result with the second portion of the conversion result to produce a combined conversion result.
摘要翻译：公开了用于捕获数据的各种系统和方法。例如，本发明的一些实施例提供了使用基于Δ-Σ的模数转换器执行第一模数转换的方法，以及使用基于SAR的模数转换器执行第二模数转换。 Δ-Σ转换器提供转换结果的第一部分，并且基于SAR的模数转换器提供转换结果的第二部分。所述方法还包括将转换结果的第一部分与转换结果的第二部分组合以产生组合转换结果。

8. 发明授权

US08308358B2 Circuit and method for beta variation compensation in single-transistor temperature sensor 有权
标题翻译：单晶体管温度传感器中β变换补偿的电路和方法
公开(公告)号：US08308358B2
公开(公告)日：2012-11-13
申请号：US12456991
申请日：2009-06-25
申请人： Jerry L. Doorenbos
发明人： Jerry L. Doorenbos
IPC分类号： G01K7/00
CPC分类号： G01K7/01 , H03F1/302 , H03F2200/447 , H03F2200/468
摘要： A circuit (1-2) for compensating for variations in the current gain β of a sensing transistor (Q1) having a collector coupled to a reference voltage (GND) includes a first current mirror (20) having an input coupled to a base of the sensing transistor. A second current mirror (21) has an input coupled to an output of the first current mirror. A current source (13) is coupled to provide emitter current for the sensing transistor. An output of the second current mirror circuit (21) feeds base current of the sensing transistor back to its emitter to cause the collector current of the sensing transistor to be precisely equal to the current (I1) provided by the current source.
摘要翻译：用于补偿电流增益变化的电路（1-2）具有耦合到参考电压（GND）的集电极的感测晶体管（Q1）包括具有耦合到感测晶体管的基极的输入的第一电流镜（20）。第二电流镜（21）具有耦合到第一电流镜的输出的输入。电流源（13）被耦合以提供感测晶体管的发射极电流。第二电流镜电路（21）的输出将感测晶体管的基极电流反馈到其发射极，以使感测晶体管的集电极电流精确地等于由电流源提供的电流（I1）。

9. 发明授权

US08164364B2 Circuitry and method for preventing base-emitter junction reverse bias in comparator differential input transistor pair 有权
公开(公告)号：US08164364B2
公开(公告)日：2012-04-24
申请号：US12804658
申请日：2010-07-27
申请人： Jerry L. Doorenbos , Sudarshan Udayashankar
发明人： Jerry L. Doorenbos , Sudarshan Udayashankar
IPC分类号： H03K5/22
CPC分类号： H03K5/08
摘要： A differential input circuit (1-1) includes first (Q0) and second (Q1) input transistors having control electrodes coupled to first (Vin+) and second (Vin−) input signals, respectively. A pass transistor (P3) is coupled between first electrodes of the first and second input transistors. First (N1) and second (N2) level shift transistors have control electrodes coupled to the first and second input signals, respectively. A voltage selector circuit (22) selects a voltage on a first electrode of one of the first and second level shift transistors according to which is at a higher voltage, and produces a corresponding control voltage (V19) on a control electrode of the pass transistor so as to limit a voltage difference between the first electrode and the control electrode of the first input transistor (Q0) when it is turned off in response to a large difference between the first and second input signals.

10. 发明申请

US20120025891A1 Bipolar transistor anti-saturation clamp using auxiliary bipolar stage, and method 有权
标题翻译：双极晶体管抗饱和钳使用辅助双极级，和方法
公开(公告)号：US20120025891A1
公开(公告)日：2012-02-02
申请号：US12804752
申请日：2010-07-28
申请人： Sudarshan Udayashankar , Jerry L. Doorenbos
发明人： Sudarshan Udayashankar , Jerry L. Doorenbos
IPC分类号： H03K5/08
CPC分类号： H03K5/08
摘要： An output stage (1-2) includes a gain circuit (Q1,Q2) for driving a base of a main transistor (Q3) having a collector coupled to an output (18) in response to an input signal V11) which also controls a base of an auxiliary transistor (Q7) having a collector coupled to the output. A clamping transistor (Q6) has a control electrode coupled to the base of the auxiliary transistor, a first electrode coupled to the output, and a second electrode coupled to provide feedback from the output via the gain circuit to the base of the main transistor and to provide feedback from the output to the base of the auxiliary transistor. When the auxiliary transistor goes into deep saturation it causes the clamping transistor to provide negative feedback from the output to the main output stage so as to prevent the main transistor from going into deep saturation.
摘要翻译：输出级（1-2）包括用于驱动具有集电极的主晶体管（Q3）的基极的增益电路（Q1，Q2），其响应于输入信号V11而耦合到输出端（18），该输入信号也控制具有耦合到输出的集电极的辅助晶体管（Q7）的基极。钳位晶体管（Q6）具有耦合到辅助晶体管的基极的控制电极，耦合到输出的第一电极和耦合以提供从输出经由增益电路到主晶体管的基极的反馈的第二电极，以及以提供从输出到辅助晶体管的基极的反馈。当辅助晶体管进入深饱和时，使钳位晶体管从输出到主输出级提供负反馈，以防止主晶体管进入深饱和。

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