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1. 发明授权

US08108508B1 Web server chip for network manageability 失效
标题翻译： Web服务器芯片，用于网络管理
公开(公告)号：US08108508B1
公开(公告)日：2012-01-31
申请号：US09102207
申请日：1998-06-22
申请人： Dave Goh , Leena Sansguiri , Paul Chou , Nandakumar Natarajan , John A. Dilley , Marcos Frid , Robert H. Hyerle , Arne Luhrs , Chandrasekar Venkatraman
发明人： Dave Goh , Leena Sansguiri , Paul Chou , Nandakumar Natarajan , John A. Dilley , Marcos Frid , Robert H. Hyerle , Arne Luhrs , Chandrasekar Venkatraman
IPC分类号： G06F15/173
CPC分类号： G06F15/7842 , G06F11/3013 , G06F11/3058 , G06F11/3065 , G06F11/3409 , G06F11/3495 , H04L67/025 , H04L69/12
摘要： A network device includes a web server chip that is connectable to a computer network. The web server chip includes an embedded processor that is programmable to function as a manageability web server, obtain manageability information about the network device and send the manageability to a network manager. The web server chip further includes an interface for communicating with an I2C bus in the network device. The embedded processor is programmable to obtain manageability information about devices connected to the I2C bus. The embedded processor is also programmable to control fan controllers, power supply controllers and other controllers connected to the I2C bus. This, in turn, allows a network manager to command the web server chip to remotely power up and power down the network device. Thus, the web server chip can perform network management functions without burdening the host processor of the network device. If network communications are performed via HTTP, the embedded processor can be programmed to implement an HTTP server, and the network manger can use a web browser and HTML files to run network management software.
摘要翻译：网络设备包括可连接到计算机网络的网络服务器芯片。网络服务器芯片包括可编程以用作可管理性web服务器的嵌入式处理器，获得关于网络设备的可管理性信息并向网络管理器发送可管理性。网络服务器芯片还包括用于与网络设备中的I2C总线通信的接口。嵌入式处理器可编程，以获得有关连接到I2C总线的设备的可管理信息。嵌入式处理器也可编程控制风扇控制器，电源控制器和连接到I2C总线的其他控制器。这反过来又允许网络管理员命令网络服务器芯片远程加电并关闭网络设备。因此，网络服务器芯片可以执行网络管理功能，而不会加重网络设备的主机处理器。如果通过HTTP执行网络通信，则嵌入式处理器可以编程为实现HTTP服务器，网络管理员可以使用Web浏览器和HTML文件来运行网络管理软件。

2. 发明授权

US06373841B1 Integrated LAN controller and web server chip 失效
标题翻译：集成LAN控制器和Web服务器芯片
公开(公告)号：US06373841B1
公开(公告)日：2002-04-16
申请号：US09102205
申请日：1998-06-22
申请人： Dave Goh , Paul Chou , Leena Sansguiri , Ronald Kroesen , Nandakumar Natarajan , John A. Dilley , Marcos Frid , Robert H. Hyerle , Arne Luhrs , Chandrasekar Venkatraman
发明人： Dave Goh , Paul Chou , Leena Sansguiri , Ronald Kroesen , Nandakumar Natarajan , John A. Dilley , Marcos Frid , Robert H. Hyerle , Arne Luhrs , Chandrasekar Venkatraman
IPC分类号： H04J302
CPC分类号： H04L41/046 , H04L41/0893 , H04L41/22 , H04L67/02
摘要： A chip for a device such as a computer includes a media access controller and an embedded processor. The embedded processor is programmed to function as a web server and provide network manageability information to a network manager. The embedded processor is also programmed to function as a LAN controller. When a packet is received by the media access controller, the embedded processor examines a destination address of the packet and routes the packet to an appropriate end point. Packets having a first unique destination address are routed to a host interface (and eventually to a host processor), and packets having a second unique address are routed to the embedded processor-functioning-as-web server. Thus, the chip allows network management and local area network communications to be performed over a single physical interface.
摘要翻译：用于诸如计算机的设备的芯片包括媒体访问控制器和嵌入式处理器。嵌入式处理器被编程为用作Web服务器并向网络管理器提供网络管理信息。嵌入式处理器也被编程为作为LAN控制器。当媒体接入控制器接收到分组时，嵌入式处理器检查分组的目的地址并将分组路由到适当的终点。具有第一唯一目的地地址的分组被路由到主机接口（并且最终到主处理器），并且具有第二唯一地址的分组被路由到嵌入式处理器功能的web服务器。因此，芯片允许通过单个物理接口执行网络管理和局域网通信。

3. 发明申请

US20080152142A1 MEMORY SCRAMBLER UNIT (MSU) 审中-公开
标题翻译：存储器SCRAMBLER UNIT（MSU）
公开(公告)号：US20080152142A1
公开(公告)日：2008-06-26
申请号：US11959300
申请日：2007-12-18
申请人： Mark Buer , Paul Chou , Lawrence J. Madar , Hon Fai (Mike) Chu
发明人： Mark Buer , Paul Chou , Lawrence J. Madar , Hon Fai (Mike) Chu
IPC分类号： H04K1/00 , G06F7/58
CPC分类号： H04W12/06 , G06F12/1408 , G06F21/79
摘要： A memory scrambler unit (MSU) is provided wherein the MSU may be within a single chip wireless transceiver operable to perform voice, data and radio frequency (RF) processing. This processing may be divided between various processing modules that access memory. This MSU may be part of a memory interface operable to provide a multi-layered scrambling approach to protect against attack scenarios on volatile memories, SRAM, and SDRAM. The MSU can be programmed to scramble configurable address regions without crossing the page, blank, or row/column boundaries, which would incur performance penalties. As an additional security measure, data may also be scrambled.
摘要翻译：提供存储器扰码器单元（MSU），其中MSU可以在可操作以执行语音，数据和射频（RF）处理的单芯片无线收发器内）。该处理可以在访问存储器的各种处理模块之间划分。该MSU可以是存储器接口的一部分，其可操作以提供多层扰频方法以防止易失性存储器，SRAM和SDRAM上的攻击情形。 MSU可以编程为加密可配置的地址区域，而不会跨越页面，空白或行/列边界，这将导致性能损失。作为额外的安全措施，数据也可能被加扰。

4. 发明申请

US20080084850A1 DISTRIBUTED MICRO INSTRUCTION SET PROCESSOR ARCHITECTURE FOR HIGH-EFFICIENCY SIGNAL PROCESSING 有权
标题翻译：分布式微指令集处理器架构实现高效信号处理
公开(公告)号：US20080084850A1
公开(公告)日：2008-04-10
申请号：US11841604
申请日：2007-08-20
申请人： Song Chen , Paul Chou , Christopher Woodthorpe , Venugopal Balasubramonian , Keith Rieken
发明人： Song Chen , Paul Chou , Christopher Woodthorpe , Venugopal Balasubramonian , Keith Rieken
IPC分类号： H04B7/216 , H04J3/06
CPC分类号： G06F15/78 , G06F9/30079 , G06F9/30083 , G06F9/30087 , G06F9/3009 , G06F9/3885 , G06F9/462 , G06F9/4881 , Y02D10/24
摘要： A wireless communication system hosts a plurality of processes in accordance with a communication protocol. The system includes application specific instruction set processors (ASISPs) that provided computation support for the process. Each ASISP is capable of executing a subset of the functions of a communication protocol. A scheduler is used to schedule the ASISPs in a time-sliced algorithm so that each ASISP supports several processes. In this architecture, the ASISP actively performs computations for one of the supported processes (active process) at any given time. The state information of each process supported by a particular ASISP is stored in a memory bank that is uniquely associated with the ASISP. When a scheduler instructs an ASISP to change which process is the active process, the state information for the inactivated process is stored in the memory bank and the state information for the newly activated process is retrieved from the memory bank.
摘要翻译：无线通信系统根据通信协议承载多个进程。该系统包括为该过程提供计算支持的特定于应用程序的指令集处理器（ASISP）。每个ASISP能够执行通信协议的功能的子集。调度程序用于以时间分片算法调度ASISP，以便每个ASISP支持多个进程。在这种体系结构中，ASISP在任何给定的时间主动执行一个受支持进程（活动进程）的计算。由特定ASISP支持的每个进程的状态信息存储在与ASISP唯一相关联的存储体中。当调度器指示ASISP改变哪个进程是活动进程时，将非活动进程的状态信息存储在存储体中，并且从存储体检索新激活的进程的状态信息。

5. 发明授权

US5956789A Screwdriver with wire stripper handle 失效
标题翻译：带拔丝手柄的螺丝刀
公开(公告)号：US5956789A
公开(公告)日：1999-09-28
申请号：US977631
申请日：1997-11-25
申请人： Paul Chou
发明人： Paul Chou
IPC分类号： B25B15/00 , B25B23/16 , B25B27/14 , B25F1/00 , B25G1/10 , H01R43/042 , H02G1/12 , B25B25/00
CPC分类号： B25B15/00 , B25B23/16 , B25B27/146 , B25F1/00 , B25G1/105 , H02G1/1214 , H01R43/0421
摘要： A screwdriver has a handle provided with a spring-biased press block secured within a recess of the handle for movement towards and away from a bottom of the recess. The press block and bottom of the recess are each provided with cooperating wire clamping and terminal clamping bodies for respectively stripping insulation from the wire and securing a terminal to a stripped end of the wire.
摘要翻译：螺丝刀具有手柄，其设置有固定在手柄的凹部内的弹簧偏置的压块，用于朝向和远离凹部的底部移动。压块和凹槽的底部均设有配合的线夹和端子夹紧体，用于分别剥离线的绝缘并将端子固定到线的剥离端。

6. 发明授权

US08826039B2 Apparatus and method for providing hardware security 有权
标题翻译：提供硬件安全性的装置和方法
公开(公告)号：US08826039B2
公开(公告)日：2014-09-02
申请号：US12714383
申请日：2010-02-26
申请人： Paul Chou , Love Kothari , Lawrence J. Madar, III
发明人： Paul Chou , Love Kothari , Lawrence J. Madar, III
IPC分类号： G06F12/14
CPC分类号： G06F21/72 , G06F12/14
摘要： A technique to provide a hardware security module that provides a secure boundary for retention of a secure key within the secure boundary and prevention of unauthorized accesses from external sources outside of the secure boundary to obtain the secure key. The hardware security module includes a security processor to unwrap and authenticate a secure key within the secure boundary to decrypt or encrypt data and to provide data through a single interface that communicates with external sources, so that all data transfers between the secure boundary, formed by the hardware security module, and external sources are transferred only through the interface. The hardware security module ensures no unwrapped key leaves the secure boundary established by the hardware security module.
摘要翻译：一种提供硬件安全模块的技术，其提供用于将安全密钥保持在安全边界内的安全边界，并防止从安全边界外部的外部源的未经授权的访问以获得安全密钥。硬件安全模块包括一个安全处理器，用于对安全边界内的安全密钥进行解包和认证，以对数据进行解密或加密，并通过与外部源通信的单一接口提供数据，从而在安全边界之间传输所有数据，由硬件安全模块和外部源仅通过接口传输。硬件安全模块确保没有解开的密钥离开硬件安全模块建立的安全边界。

7. 发明申请

US20110067110A1 METHOD AND SYSTEM FOR HARDWARE ENFORCED VIRTUALIZATION IN AN INTEGRATED CIRCUIT 有权
标题翻译：在集成电路中硬件实现虚拟化的方法和系统
公开(公告)号：US20110067110A1
公开(公告)日：2011-03-17
申请号：US12559154
申请日：2009-09-14
申请人： John Markey , Love Kothari , Paul Chou
发明人： John Markey , Love Kothari , Paul Chou
IPC分类号： G06F21/20 , G06F9/00
CPC分类号： G06F21/575 , G06F21/74 , G06F2221/2105
摘要： Aspects of a method and system for hardware enforced virtualization in an integrated circuit are provided. In this regard, a mode of operation of an integrated circuit may be controlled such that the integrated circuit alternates between a secure mode of operation and an open mode of operation. Various resources of the integrated circuit may be designated as open or secure, and secure resources may be made inaccessible while the integrated circuit operates in the open mode. Access to the secure resources may be controlled based on a configuration of one or more registers and/or switching elements. Resources designated as secure may comprise, for example, a one-time-programmable memory. The integrated circuit may comprise ROM and/or one-time-programmable memory that stores one or more instructions, wherein execution of the one or more instructions may control transitions between the secure mode and the open mode.
摘要翻译：提供了集成电路中用于硬件强制虚拟化的方法和系统的方面。在这方面，可以控制集成电路的操作模式，使得集成电路在安全操作模式和开放操作模式之间交替。集成电路的各种资源可以被指定为开放的或安全的，并且当集成电路在开放模式下操作时，可以使安全的资源变得不可访问。可以基于一个或多个寄存器和/或开关元件的配置来控制对安全资源的访问。指定为安全的资源可以包括例如一次性可编程存储器。集成电路可以包括存储一个或多个指令的ROM和/或一次可编程存储器，其中一个或多个指令的执行可以控制安全模式和打开模式之间的转换。

8. 发明申请

US20110066835A1 METHOD AND SYSTEM FOR SECURELY PROTECTING A SEMICONDUCTOR CHIP WITHOUT COMPROMISING TEST AND DEBUG CAPABILITIES 失效
标题翻译：在不影响测试和调试能力的情况下安全地保护半导体芯片的方法和系统
公开(公告)号：US20110066835A1
公开(公告)日：2011-03-17
申请号：US12559242
申请日：2009-09-14
申请人： Love Kothari , Paul Chou , John Markey
发明人： Love Kothari , Paul Chou , John Markey
IPC分类号： G06F15/177
CPC分类号： G06F21/33 , G06F11/3648
摘要： A semiconductor chip may be operable to block the debug interfaces when the semiconductor chip boots up from the boot read-only memory (ROM). The semiconductor chip may be operable to authenticate a debug certificate received by the semiconductor chip and enable one or more debug interfaces in the semiconductor chip based on the information resulting from the authentication of the debug certificate. The debug certificate may be in a form of a cryptographic public key certificate. A unique device ID which may be generated at boot and stored in the memory may be used by the semiconductor chip to authenticate the debug certificate. The device ID may be generated using the cryptographic public key that is stored in the one-time programmable (OTP) memory in the semiconductor chip and a cryptographic hash algorithm.
摘要翻译：当半导体芯片从引导只读存储器（ROM）启动时，半导体芯片可以用于阻止调试接口。半导体芯片可以用于对由半导体芯片接收到的调试证书进行认证，并且基于从调试证书的认证得到的信息来启用半导体芯片中的一个或多个调试接口。调试证书可以是加密公钥证书的形式。半导体芯片可以在启动时产生并存储在存储器中的独特的设备ID用于认证调试证书。可以使用存储在半导体芯片中的一次可编程（OTP）存储器中的密码公钥和密码散列算法来生成设备ID。

9. 发明授权

US08918575B2 Method and system for securely programming OTP memory 有权
标题翻译：用于安全编程OTP存储器的方法和系统
公开(公告)号：US08918575B2
公开(公告)日：2014-12-23
申请号：US12559221
申请日：2009-09-14
申请人： John Markey , Love Kothari , Paul Chou
发明人： John Markey , Love Kothari , Paul Chou
IPC分类号： G06F12/00 , G06F21/57
CPC分类号： G06F21/572
摘要： A semiconductor chip may be operable to receive and copy an OTP programming vector presented by the semiconductor chip programming device into its memory after it boots up from the boot read-only memory (ROM). The OTP programming vector which is a computer program may comprise an encrypted data to be programmed into the one-time programmable (OTP) memory in the semiconductor chip and may be signed with an electronic signature. The semiconductor chip may be operable to authenticate the OTP programming vector in the memory. The authenticated OTP programming vector in the memory may be executed to decrypt the data and program the data in a random data format into the OTP memory and then report the status via one or more general purpose input/output (GPIO) pins on the semiconductor chip.
摘要翻译：半导体芯片可以在从引导只读存储器（ROM）启动之后，将由半导体芯片编程设备呈现的OTP编程向量接收并复制到其存储器中。作为计算机程序的OTP编程向量可以包括要编程到半导体芯片中的一次可编程（OTP）存储器中的加密数据，并且可以用电子签名来签名。半导体芯片可以用于对存储器中的OTP编程向量进行认证。可以执行存储器中的认证的OTP编程向量来解密数据并将数据以随机数据格式编程到OTP存储器中，然后通过半导体芯片上的一个或多个通用输入/输出（GPIO）引脚报告状态。

10. 发明授权

US08650633B2 Integrated circuit for preventing chip swapping and/or device cloning in a host device 有权
标题翻译：用于在主机设备中防止芯片交换和/或设备克隆的集成电路
公开(公告)号：US08650633B2
公开(公告)日：2014-02-11
申请号：US13250529
申请日：2011-09-30
申请人： Love Kothari , Paul Chou
发明人： Love Kothari , Paul Chou
IPC分类号： G06F21/00
CPC分类号： H03L7/0802 , G06F1/26 , G06F1/32 , G06F1/3203 , G06F1/3228 , G06F12/14 , G06F21/44 , H01L2924/0002 , H03K3/0315 , H03K3/037 , H03K3/0375 , H03K5/133 , H03K19/01 , H03K2005/00019 , H03K2005/00026 , H03K2005/00058 , H03L7/097 , H03L7/0997 , H01L2924/00
摘要： An integrated circuit is disclosed that can be included in a host electronic device that can be commonly manufactured, where the integrated circuit can be designated (“locked”) for a specific manufacturer, thereby substantially reducing the likelihood that a third party will be able to successfully clone a host electronic device manufactured by the specific manufacturer and/or swap the chip containing the integrated circuit for one having more enabled features. The integrated circuit includes an ID module that can be programmed after fabrication. Components within the integrated circuit designate manufacturer-specific configurations (e.g., address mapping, pin routing and/or vital function releasing) based on the programmed manufacturer ID. As a result, once the integrated circuit has been programmed with the manufacturer ID, the integrated circuit will function correctly only within a host device manufactured by the manufacturer associated with the programmed manufacturer ID.
摘要翻译：公开了一种集成电路，其可以被包括在可以通常制造的主机电子设备中，其中可以为特定制造商指定（“锁定”）集成电路，从而显着降低第三方将能够成功克隆由特定制造商制造的主机电子设备和/或将包含集成电路的芯片交换为具有更多启用特征的芯片。集成电路包括可在制造后编程的ID模块。集成电路中的组件基于编程的制造商ID指定制造商特定的配置（例如，地址映射，引脚布线和/或重要功能释放）。因此，一旦集成电路已经用制造商ID编程，集成电路将仅在制造商制造的与编程的制造商ID相关联的主机设备中正常工作。

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