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1. 发明申请

US20060133156A1 Systems for comprehensive erase verification in non-volatile memory 有权
公开(公告)号：US20060133156A1
公开(公告)日：2006-06-22
申请号：US11316475
申请日：2005-12-21
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey Lutze , Jun Wan
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

2. 发明申请

US20060098494A1 Comprehensive erase verification for non-volatile memory 有权
公开(公告)号：US20060098494A1
公开(公告)日：2006-05-11
申请号：US11316119
申请日：2005-12-21
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey Lutze , Jun Wan
IPC分类号： G11C16/04
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

3. 发明申请

US20060098495A1 Systems for comprehensive erase verification in non-volatile memory 有权
公开(公告)号：US20060098495A1
公开(公告)日：2006-05-11
申请号：US11316162
申请日：2005-12-21
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey Lutze , Jun Wan
IPC分类号： G11C16/04
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

4. 发明申请

US20060098493A1 Comprehensive erase verification for non-volatile memory 有权
公开(公告)号：US20060098493A1
公开(公告)日：2006-05-11
申请号：US11316069
申请日：2005-12-21
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey Lutze , Jun Wan
IPC分类号： G11C16/04
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

5. 发明申请

US20050265081A1 COMPREHENSIVE ERASE VERIFICATION FOR NON-VOLATILE MEMORY 失效
标题翻译：用于非易失性存储器的综合擦除验证
公开(公告)号：US20050265081A1
公开(公告)日：2005-12-01
申请号：US10857245
申请日：2004-05-28
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey Lutze , Jun Wan
IPC分类号： G11C16/34 , G11C16/04
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.
摘要翻译：根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。这样的字符串可能是有缺陷的，并被映射出存储器件。

6. 发明授权

US07463532B2 Comprehensive erase verification for non-volatile memory 有权
标题翻译：非易失性存储器的全面擦除验证
公开(公告)号：US07463532B2
公开(公告)日：2008-12-09
申请号：US11316119
申请日：2005-12-21
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
IPC分类号： G11C11/34
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.
摘要翻译：根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。这样的字符串可能是有缺陷的，并被映射出存储器件。

7. 发明授权

US07512014B2 Comprehensive erase verification for non-volatile memory 有权
标题翻译：非易失性存储器的全面擦除验证
公开(公告)号：US07512014B2
公开(公告)日：2009-03-31
申请号：US11316069
申请日：2005-12-21
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
IPC分类号： G11C11/34
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.
摘要翻译：根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。这样的字符串可能是有缺陷的，并被映射出存储器件。

8. 发明授权

US07508720B2 Systems for comprehensive erase verification in non-volatile memory 有权
标题翻译：非易失性存储器中的全面擦除验证系统
公开(公告)号：US07508720B2
公开(公告)日：2009-03-24
申请号：US11316475
申请日：2005-12-21
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
IPC分类号： G11C11/34
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.
摘要翻译：根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。这样的字符串可能是有缺陷的，并被映射出存储器件。

9. 发明授权

US07450435B2 Systems for comprehensive erase verification in non-volatile memory 有权
标题翻译：非易失性存储器中的全面擦除验证系统
公开(公告)号：US07450435B2
公开(公告)日：2008-11-11
申请号：US11316162
申请日：2005-12-21
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
IPC分类号： G11C11/34
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.
摘要翻译：根据各种实施例的系统和方法可以提供非易失性半导体存储器中的全面擦除验证和缺陷检测。在一个实施例中，使用多个测试条件来验证擦除一组存储元件的结果，以更好地检测组中的有缺陷和/或不充分擦除的存储元件。例如，擦除NAND串的结果可以通过在多个方向上测试字符串的充电来验证，其中存储元件被偏置为在擦除状态下导通。如果一串存储元件通过第一个测试过程或操作，但是失败了第二个测试过程或操作，则可以确定该字符串已经失效了擦除过程并且可能是有缺陷的。通过在多个方向上测试串的充电或导通，在一组条件下被屏蔽的串的任何晶体管中的缺陷可能在第二组偏置条件下暴露。例如，字符串可以传递擦除验证操作，然后被读取为包括一个或多个编程的存储元件。这样的字符串可能是有缺陷的，并被映射出存储器件。

10. 发明授权

US07009889B2 Comprehensive erase verification for non-volatile memory 失效
公开(公告)号：US07009889B2
公开(公告)日：2006-03-07
申请号：US10857245
申请日：2004-05-28
申请人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
发明人： Dat Tran , Kiran Ponnuru , Jian Chen , Jeffrey W. Lutze , Jun Wan
IPC分类号： G11C16/04
CPC分类号： G11C16/3468
摘要： Systems and methods in accordance with various embodiments can provide for comprehensive erase verification and defect detection in non-volatile semiconductor memory. In one embodiment, the results of erasing a group of storage elements is verified using a plurality of test conditions to better detect defective and/or insufficiently erased storage elements of the group. For example, the results of erasing a NAND string can be verified by testing charging of the string in a plurality of directions with the storage elements biased to turn on if in an erased state. If a string of storage elements passes a first test process or operation but fails a second test process or operation, the string can be determined to have failed the erase process and possibly be defective. By testing charging or conduction of the string in a plurality of directions, defects in any transistors of the string that are masked under one set of conditions may be exposed under a second set of bias conditions. For example, a string may pass an erase verification operation but then be read as including one or more programmed storage elements. Such a string can be defective and mapped out of the memory device.

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