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1. 发明授权

US08248170B2 Stabilized digital quadrature oscillator 有权
标题翻译：稳定数字正交振荡器
公开(公告)号：US08248170B2
公开(公告)日：2012-08-21
申请号：US12952154
申请日：2010-11-22
申请人： Dariush Dabiri , Dongwoon Bai , Nils Graef , Wenwei Pan
发明人： Dariush Dabiri , Dongwoon Bai , Nils Graef , Wenwei Pan
IPC分类号： H03K3/03
CPC分类号： G06F1/022
摘要： A stabilized quadrature oscillator providing consistently high signal quality is disclosed. The stabilized quadrature oscillator includes an iterative quadrature oscillator and a quadrature signal stabilizer. The iterative quadrature oscillator generates an iterative cosine signal and an iterative sine signal using a stabilized cosine signal and a stabilized sine signal from the quadrature signal stabilizer. The quadrature signal stabilizer generates the stabilized cosine signal and the stabilized sine signal based on an energy measure of the iterative cosine signal and the iterative sine signal. Specifically, if the energy measure is less than a low threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a greater magnitude than the iterative sine signal and the iterative cosine signal, respectively. Conversely, if the energy measure is greater than a high threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a lesser magnitude than the iterative sine signal and the iterative cosine signal, respectively.
摘要翻译：公开了一种提供一致的高信号质量的稳定的正交振荡器。稳定的正交振荡器包括迭代正交振荡器和正交信号稳定器。迭代正交振荡器使用稳定余弦信号和来自正交信号稳定器的稳定正弦信号产生迭代余弦信号和迭代正弦信号。正交信号稳定器基于迭代余弦信号和迭代正弦信号的能量测量值产生稳定的余弦信号和稳定的正弦信号。具体地说，如果能量测量小于低阈值，则正交信号稳定器分别产生稳定的正弦信号和稳定的余弦信号，以具有比迭代正弦信号和迭代余弦信号更大的幅度。相反，如果能量测量值大于高阈值，则正交信号稳定器分别产生稳定正弦信号和稳定余弦信号，其幅度分别小于迭代正弦信号和迭代余弦信号。

2. 发明申请

US20120126903A1 Stabilized Digital Quadrature Oscillator 有权
标题翻译：稳定数字正交振荡器
公开(公告)号：US20120126903A1
公开(公告)日：2012-05-24
申请号：US12952154
申请日：2010-11-22
申请人： Dariush Dabiri , Dongwoon Bai , Nils Graef , Wenwei Pan
发明人： Dariush Dabiri , Dongwoon Bai , Nils Graef , Wenwei Pan
IPC分类号： H03B27/00
CPC分类号： G06F1/022
摘要： A stabilized quadrature oscillator providing consistently high signal quality is disclosed. The stabilized quadrature oscillator includes an iterative quadrature oscillator and a quadrature signal stabilizer. The iterative quadrature oscillator generates an iterative cosine signal and an iterative sine signal using a stabilized cosine signal and a stabilized sine signal from the quadrature signal stabilizer. The quadrature signal stabilizer generates the stabilized cosine signal and the stabilized sine signal based on an energy measure of the iterative cosine signal and the iterative sine signal. Specifically, if the energy measure is less than a low threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a greater magnitude than the iterative sine signal and the iterative cosine signal, respectively. Conversely, if the energy measure is greater than a high threshold then the quadrature signal stabilizer generates the stabilized sine signal and the stabilized cosine signal to have a lesser magnitude than the iterative sine signal and the iterative cosine signal, respectively.
摘要翻译：公开了一种提供一致的高信号质量的稳定的正交振荡器。稳定的正交振荡器包括迭代正交振荡器和正交信号稳定器。迭代正交振荡器使用稳定余弦信号和来自正交信号稳定器的稳定正弦信号产生迭代余弦信号和迭代正弦信号。正交信号稳定器基于迭代余弦信号和迭代正弦信号的能量测量值产生稳定的余弦信号和稳定的正弦信号。具体地说，如果能量测量小于低阈值，则正交信号稳定器分别产生稳定的正弦信号和稳定的余弦信号，以具有比迭代正弦信号和迭代余弦信号更大的幅度。相反，如果能量测量值大于高阈值，则正交信号稳定器分别产生稳定正弦信号和稳定余弦信号，其幅度分别小于迭代正弦信号和迭代余弦信号。

3. 发明授权

US06415413B1 Configurable Reed-Solomon controller and method 有权
标题翻译：可配置的Reed-Solomon控制器和方法
公开(公告)号：US06415413B1
公开(公告)日：2002-07-02
申请号：US09336630
申请日：1999-06-18
申请人： Wenwei Pan , Yue-Peng Zheng
发明人： Wenwei Pan , Yue-Peng Zheng
IPC分类号： H03M1315
CPC分类号： H03M13/6516 , H03M13/1515 , H03M13/153 , H03M13/1555 , H03M13/35
摘要： Disclosed is an RS decoder controller and method, the system comprising a codeword length register to indicate a number of symbols in a number of RS codewords to be decoded by the RS decoder, a error correction capability configuration register to indicate a number of error symbols that are corrected by the RS decoder, and a modulation scheme associated register to indicate a modulation scheme associated employed to generate the RS codewords. The RS decoder controller further includes a number of state machines to control the operation of a Galois field computation unit in the RS decoder.
摘要翻译：公开了一种RS解码器控制器和方法，该系统包括：码字长度寄存器，用于指示由RS解码器解码的多个RS码字中的符号数;纠错能力配置寄存器，用于指示多个错误符号，由RS解码器和调制方案相关联的寄存器来校正，以指示用于生成RS码字的相关调制方案。 RS解码器控制器还包括多个状态机以控制RS解码器中的伽罗瓦域计算单元的操作。

4. 发明授权

US06370671B1 Configurable decoder and method for decoding a reed-solomon codeword 有权
标题翻译：用于解码簧片专用码字的可配置解码器和方法
公开(公告)号：US06370671B1
公开(公告)日：2002-04-09
申请号：US09335975
申请日：1999-06-18
申请人： Wenwei Pan , Yue-Peng Zheng
发明人： Wenwei Pan , Yue-Peng Zheng
IPC分类号： H03M1300
CPC分类号： H03M13/6516 , H03M13/1515 , H03M13/153 , H03M13/1555
摘要： Disclosed is a configurable Reed-Solomon (RS) decoder that comprises a parallel multiply accumulator having a data input to receive at least one RS codeword, the parallel multiply accumulator being configured to generate a syndrome array from the RS codeword. The configurable RS decoder also includes a Galois field computation unit coupled to the parallel multiply accumulator, and an RS decoder controller coupled to the parallel multiply accumulator and the Galois field computation unit, wherein the RS decoder controller controls the operation of the parallel multiply accumulator and the Galois field computation unit. The RS decoder may be configured for different numbers of symbols in the RS codewords, parity symbols in the RS codewords, and modulation types employed in creating the RS codewords.
摘要翻译：公开了一种可配置的Reed-Solomon（RS）解码器，其包括具有数据输入以接收至少一个RS码字的并行乘法累加器，并行乘法累加器被配置为从RS码字生成校正子阵列。可配置RS解码器还包括耦合到并行乘法累加器的伽罗瓦域计算单元和耦合到并行乘法累加器和伽罗瓦域计算单元的RS解码器控制器，其中RS解码器控制器控制并行乘法累加器的操作，伽罗瓦域计算单元。 RS解码器可以被配置用于RS码字中的不同数量的符号，RS码字中的奇偶校验符号以及用于创建RS码字的调制类型。

5. 发明授权

US06353909B1 Configurable encoder and method for generating a Reed-Solomon codeword 有权
标题翻译：用于生成里德 - 所罗门码字的可配置编码器和方法
公开(公告)号：US06353909B1
公开(公告)日：2002-03-05
申请号：US09309462
申请日：1999-05-11
申请人： Daniel Amrany , Wenwei Pan , William Santulli , Yue-Peng Zheng
发明人： Daniel Amrany , Wenwei Pan , William Santulli , Yue-Peng Zheng
IPC分类号： H03M1315
CPC分类号： H03M13/6516 , H03M13/1515 , H03M13/158
摘要： Disclosed is a configurable Reed-Solomon encoder and method. The configurable Reed-Solomon encoder comprises a multiplexed multiplier-accumulator, a parallel latch bank operatively coupled to the multiplexed multiplier-accumulator, a data/parity multiplexer coupled to the parallel latch bank, and an encoder controller operatively coupled to, and controlling the operation of, the multiplexed multiplier-accumulator, the parallel latch bank, and the data/parity multiplexer. The configurable Reed-Solomon encoder is preferably implemented in an application specific integrated circuit (ASIC), although it may be implemented in software executed by a high-speed digital signal processor, etc.
摘要翻译：公开了一种可配置的Reed-Solomon编码器和方法。可配置Reed-Solomon编码器包括多路复用乘法器累加器，可操作地耦合到多路复用乘法器累加器的并行锁存器组，耦合到并行锁存器组的数据/奇偶校验多路复用器，以及可操作地耦合到并控制操作的编码器控制器多路复用乘法器累加器，并行锁存器组和数据/奇偶校验多路复用器。可配置的Reed-Solomon编码器优选地在专用集成电路（ASIC）中实现，尽管它可以由由高速数字信号处理器等执行的软件来实现。

6. 发明授权

US06412090B1 Galois field computation system and method 有权
标题翻译：伽罗瓦域计算系统和方法
公开(公告)号：US06412090B1
公开(公告)日：2002-06-25
申请号：US09336626
申请日：1999-06-18
申请人： Wenwei Pan , Yue-Peng Zheng
发明人： Wenwei Pan , Yue-Peng Zheng
IPC分类号： H03M1315
CPC分类号： H03M13/6516 , H03M13/1515 , H03M13/153 , H03M13/1555
摘要： Disclosed is a configurable Galois field computation system and method, the system comprising a read bus and a write bus with a memory coupled therebetween. In addition, a logical circuit is coupled between the read and write busses, the logical circuit having a number of data calculation configurations that are established to generate an n symbol codeword from a number of symbols in a syndrome array. The logical circuit is placed in the various data calculation configurations in order to perform the various operations involved with Reed-Solomon decoding.
摘要翻译：公开了一种可配置的伽罗瓦域计算系统和方法，该系统包括读总线和写总线，其间耦合有存储器。此外，逻辑电路耦合在读和总线之间，逻辑电路具有多个数据计算配置，其被建立以从校正子阵列中的多个符号生成n个符号码字。将逻辑电路置于各种数据计算配置中，以执行Reed-Solomon解码所涉及的各种操作。

7. 发明授权

US06971057B1 System and method for efficient convolutional interleaving/de-interleaving 有权
标题翻译：用于高效卷积交织/解交织的系统和方法
公开(公告)号：US06971057B1
公开(公告)日：2005-11-29
申请号：US09793172
申请日：2001-02-26
申请人： Marc Delvaux , Wenwei Pan , Jian Wang
发明人： Marc Delvaux , Wenwei Pan , Jian Wang
IPC分类号： H03M13/03 , H03M13/27
CPC分类号： H03M13/2732
摘要： A memory optimized system and method for data interleaving/de-interleaving are disclosed. A data interleaver/de-interleaver may be implemented with a memory device and an improved data interleaver/de-interleaver. The improved data interleaver/de-interleaver may be implemented with a controller, a first array, and a second array. The first array identifies a maximum depth value for each of a plurality of memory segments responsive to both a block data length and the desired interleaving/de-interleaving depth. The second array comprises an index associated with each of the plurality of memory segments that may be used to derive write and read addresses. In its broadest terms, the method can be described as: identifying a block data length, N, and an interleaver/de-interleaver depth, D; initializing a set of pointers associated with each of N memory segments; initializing a set of pointer maximum values responsive to the relative magnitude of N and D, identifying a memory index responsive to a base address and the set of pointer maximum values; using a memory segment identifier, a word identifier, and a byte identifier along with the memory index and the pointers to write/read the bytes of code words.
摘要翻译：公开了一种用于数据交织/解交织的存储器优化系统和方法。数据交织器/解交织器可以用存储器件和改进的数据交织器/解交织器来实现。改进的数据交织器/解交织器可以用控制器，第一阵列和第二阵列来实现。第一阵列响应于块数据长度和期望的交织/解交织深度来识别多个存储器段中的每一个的最大深度值。第二阵列包括与可用于导出写入和读取地址的多个存储器段中的每一个相关联的索引。在其最广泛的术语中，该方法可以被描述为：识别块数据长度N和交织器/解交织器深度D; 初始化与N个存储器段中的每一个相关联的一组指针; 响应于N和D的相对幅度来初始化一组指针最大值，识别响应于基地址和指针最大值集合的存储器索引; 使用存储器段标识符，字标识符和字节标识符以及存储器索引和指针来写入/读取码字的字节。

8. 发明授权

US06536001B1 Circuit and method for convolutional interleaving using a single modulo operation 有权
标题翻译：使用单模运算进行卷积交错的电路和方法
公开(公告)号：US06536001B1
公开(公告)日：2003-03-18
申请号：US09524464
申请日：2000-03-13
申请人： Lujing Cai , Wenwei Pan , Jian Wang
发明人： Lujing Cai , Wenwei Pan , Jian Wang
IPC分类号： H03M1327
CPC分类号： H03M13/2732
摘要： A circuit and method that provides a one-step real time pointer for interleaving/deinterleaving that uses a single modulo operation is disclosed. The single modulo pointer of the present invention may be used to increase data throughput through a data interleaver/deinterleaver. A memory address pointer consistent with the present invention may be implemented with a multiplexer, an adder, a counter, and a modulo operator. A method for convolutional interleaving/deinterleaving is also disclosed.
摘要翻译：公开了一种提供用于使用单个模运算的交织/解交织的一步实时指针的电路和方法。本发明的单模指针可以用于通过数据交织器/去交织器来增加数据吞吐量。与本发明一致的存储器地址指针可以用多路复用器，加法器，计数器和模运算符来实现。还公开了卷积交织/去交织的方法。

9. 发明授权

US06480976B1 System and method for resource optimized integrated forward error correction in a DMT communication system 有权
标题翻译：在DMT通信系统中资源优化的集成前向纠错系统和方法
公开(公告)号：US06480976B1
公开(公告)日：2002-11-12
申请号：US09523747
申请日：2000-03-13
申请人： Wenwei Pan , Jian Wang
发明人： Wenwei Pan , Jian Wang
IPC分类号： G06F1100
CPC分类号： H04L1/0057 , H04L1/0002 , H04L1/0043 , H04L1/0052 , H04L1/007 , H04L1/0071
摘要： A resource optimized interleaving/deinterleaving system comprising a Reed-Solomon encoder, a Reed-Solomon decoder, a state machine, and a memory is disclosed. Reed-Solomon encoded fastpath data is stored in memory. A stream of interleaved data with predefined parameters S, the number of DMT symbols per each Reed-Solomon codeword, D, the interleaving depth, and N, the block length is written into system memory at an adaptable rate determined by the Reed-Solomon encoder. The previously stored Reed-Solomon encoded fastpath data is automatically reassembled and buffered with the interleaved data to form appropriate DMT transmission symbols. The DMT transmission symbols are then read out of the system memory at a rate determined by the next processing function, i.e., tone ordering. A method of using one Reed-Solomon encoder/decoder with the integrated interleaving/deinterleaving system to support dual single latency DMT systems is also disclosed.
摘要翻译：公开了一种包括Reed-Solomon编码器，Reed-Solomon解码器，状态机和存储器的资源优化交织/解交织系统。 Reed-Solomon编码的快速路径数据存储在内存中。具有预定义参数S的交织数据流，每个Reed-Solomon码字的DDMT符号的数目D，交织深度N和块长度以由Reed-Solomon编码器确定的适应速率被写入系统存储器。先前存储的Reed-Solomon编码的快速路径数据被自动重新组装并用交织的数据缓冲以形成适当的DMT传输符号。然后，DMT传输符号以由下一个处理功能确定的速率即音调排序从系统存储器中读出。还公开了使用一个Reed-Solomon编码器/解码器与集成交织/解交织系统来支持双单等待时间DMT系统的方法。

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