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1. 发明申请

US20070176208A1 Hosting structure of nanometric elements and corresponding manufacturing method 有权
标题翻译：纳米元素的主机结构及相应的制造方法
公开(公告)号：US20070176208A1
公开(公告)日：2007-08-02
申请号：US11215348
申请日：2005-08-30
申请人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
发明人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
IPC分类号： H01L27/10
CPC分类号： H01L51/0021 , G11C2213/77 , H01L27/285 , H01L51/0595 , Y10S257/90 , Y10S977/712 , Y10S977/72 , Y10S977/722 , Y10S977/723
摘要： A hosting structure of nanometric components is described comprising a substrate, a first multi-spacer level comprising a first plurality of spacers including first conductive spacers parallel to each other, and at least a second multi-spacer level realized above said first multi-spacer level and comprising a second plurality of spacers arranged transversally to said first plurality of spacers and including at least a lower discontinuous insulating layer and an upper layer, including in turn second conductive spacers. In particular, each pair of spacers of the second multi-spacer level defines with a spacer of the first multi-spacer level a plurality of nanometric hosting seats having at least a first and a second conduction terminal realized by portions of the first conductive spacers and of the second conductive spacers faced in the hosting seats. A method for manufacturing such a structure is also described.
摘要翻译：描述了纳米级元件的托管结构，其包括衬底，第一多间隔物层，包括第一多个间隔物，其包括彼此平行的第一导电间隔物，以及在所述第一多间隔物层上方实现的至少第二多间隔物水平并且包括横向于所述第一多个间隔件布置的第二多个间隔件，并且至少包括下部不连续绝缘层和上层，其又包括第二导电间隔件。特别地，第二多间隔物级别的每对间隔物限定第一多间隔物层的间隔物，多个纳米托管座具有至少第一和第二导电端子，该第一和第二导电端子由第一导电间隔物的部分实现，的第二导电隔离物面向主机座。还描述了制造这种结构的方法。

2. 发明申请

US20060051946A1 Method for realizing a hosting structure of nanometric elements 有权
标题翻译：实现纳米元件托管结构的方法
公开(公告)号：US20060051946A1
公开(公告)日：2006-03-09
申请号：US11215297
申请日：2005-08-30
申请人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
发明人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
IPC分类号： H01L21/3205 , H01L21/20
CPC分类号： H01L21/0337 , H01L21/0338 , Y10S977/70 , Y10S977/701
摘要： Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the block-seed a first layer, of predetermined thickness of a second material, and subsequently selectively and anisotropically etching it to form a spacer-seed adjacent to the side wall. The cycle of deposition and selective etching steps of a predetermined material are repeated n times (n≧2), with at least one spacer formed in each cycle. This predetermined material is different for each pair of consecutive depositions. The above n steps provides at least one multilayer body. Further selective etching removes every other spacers to provide a plurality of nanometric hosting seats, which forms contact terminals for a plurality of molecular transistors hosted in said hosting seats.
摘要翻译：制造纳米元件的托盘结构的方法，包括以下步骤：在第一材料的基片的上表面上沉积具有至少一个侧壁的块状晶种。在至少一部分的悲伤表面上和块状种子上沉积具有预定厚度的第二材料的第一层，并随后选择性地和各向异性地蚀刻它以形成邻近侧壁的间隔物种子。重复n次（n> = 2）预定材料的沉积循环和选择性蚀刻步骤，每个循环中形成至少一个间隔物。该预定材料对于每对连续沉积物是不同的。上述n个步骤提供至少一个多层体。进一步的选择性蚀刻除去每隔一个间隔物以提供多个纳米托管座，其形成托管在所述托管座中的多个分子晶体管的接触端子。

3. 发明授权

US07952173B2 Nanometric device with a hosting structure of nanometric elements 有权
标题翻译：具有纳米元件托管结构的纳米仪器
公开(公告)号：US07952173B2
公开(公告)日：2011-05-31
申请号：US12204688
申请日：2008-09-04
申请人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
发明人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
IPC分类号： H01L29/06
CPC分类号： H01L21/0337 , H01L21/0338 , Y10S977/70 , Y10S977/701
摘要： A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats.
摘要翻译：一种纳米装置，包括基底; 导电材料的多个导电间隔物，每个导电间隔物布置在衬底的顶部并横向于衬底，导电间隔物包括相应的一对导电间隔物，每个导电间隔物限定各自的托架座位，每个主体座椅的宽度小于30nm; 以及分别容纳在托管座椅中的多个纳米元件。

4. 发明申请

US20060051919A1 Nanometric structure and corresponding manufacturing method 有权
标题翻译：纳米结构及相应的制造方法
公开(公告)号：US20060051919A1
公开(公告)日：2006-03-09
申请号：US11215296
申请日：2005-08-30
申请人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
发明人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
IPC分类号： H01L21/8242
CPC分类号： H01L51/0021 , H01L51/0595 , Y10S977/712 , Y10S977/781
摘要： A hosting structure of nanometric components is described advantageously comprising: a substrate; n array levels on said substrate, with n≧2, arranged consecutively on growing and parallel planes, each including a plurality of conductive spacers alternated with a plurality of insulating spacers and substantially perpendicular to said substrate, with definition between consecutive conductive spacers of at least a gap, conductive spacers of consecutive array levels lying on distinct and parallel planes, said gaps of different array levels being at least partially aligned along a direction substantially perpendicular to said substrate with definition of a plurality of transversal hosting seats extended along said direction and suitable for hosting at least a nanometric component. A nanometric electronic device is also described comprising such a hosting structure and a method for realizing it.
摘要翻译：描述了纳米组件的托管结构，其有利地包括：衬底; 所述衬底上的n个阵列电平，n> = 2，在生长和平行平面上连续布置，每个平面包括多个导电间隔物，其与多个绝缘间隔物交替并且基本上垂直于所述衬底，至少一个间隙，位于不同平行平面上的连续阵列电平的导电间隔物，不同阵列电平的所述间隙沿着基本上垂直于所述衬底的方向至少部分对准，定义了沿着所述方向延伸的多个横向主持座，适合托管至少一个纳米元件。还描述了一种纳米电子设备，其包括这样的托管结构和用于实现它的方法。

5. 发明授权

US07432120B2 Method for realizing a hosting structure of nanometric elements 有权
标题翻译：实现纳米元件托管结构的方法
公开(公告)号：US07432120B2
公开(公告)日：2008-10-07
申请号：US11215297
申请日：2005-08-30
申请人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
发明人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
IPC分类号： H01L21/00 , H01L21/311
CPC分类号： H01L21/0337 , H01L21/0338 , Y10S977/70 , Y10S977/701
摘要： Method for manufacturing a hosting structure of nanometric elements comprising the steps of depositing on an upper surface of a substrate, of a first material, a block-seed having at least one side wall. Depositing on at least one portion of sad surface and on the block-seed a first layer, of predetermined thickness of a second material, and subsequently selectively and anisotropically etching it to form a spacer-seed adjacent to the side wall. The cycle of deposition and selective etching steps of a predetermined material are repeated n times (n≧2), with at least one spacer formed in each cycle. This predetermined material is different for each pair of consecutive depositions. The above n steps provides at least one multilayer body. Further selective etching removes every other spacers to provide a plurality of nanometric hosting seats, which forms contact terminals for a plurality of molecular transistors hosted in said hosting seats.
摘要翻译：制造纳米元件的托盘结构的方法，包括以下步骤：在第一材料的基片的上表面上沉积具有至少一个侧壁的块状晶种。在所述表面和块状种子的至少一部分上沉积具有预定厚度的第二材料的第一层，随后选择性地和各向异性地蚀刻它，以形成邻近侧壁的间隔物种子。重复n次（n> = 2）预定材料的沉积循环和选择性蚀刻步骤，每个循环中形成至少一个间隔物。该预定材料对于每对连续沉积物是不同的。上述n个步骤提供至少一个多层体。进一步的选择性蚀刻除去每隔一个间隔物以提供多个纳米托管座，其形成托管在所述托管座中的多个分子晶体管的接触端子。

6. 发明授权

US07834344B2 Nanometric structure and corresponding manufacturing method 有权
标题翻译：纳米结构及相应的制造方法
公开(公告)号：US07834344B2
公开(公告)日：2010-11-16
申请号：US11215296
申请日：2005-08-30
申请人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
发明人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
IPC分类号： H01L25/10 , H01L45/00
CPC分类号： H01L51/0021 , H01L51/0595 , Y10S977/712 , Y10S977/781
摘要： A hosting structure of nanometric components is described advantageously comprising: a substrate; n array levels on said substrate, with n≧2, arranged consecutively on growing and parallel planes, each including a plurality of conductive spacers alternated with a plurality of insulating spacers and substantially perpendicular to said substrate, with definition between consecutive conductive spacers of at least a gap, conductive spacers of consecutive array levels lying on distinct and parallel planes, said gaps of different array levels being at least partially aligned along a direction substantially perpendicular to said substrate with definition of a plurality of transversal hosting seats extended along said direction and suitable for hosting at least a nanometric component. A nanometric electronic device is also described comprising such a hosting structure and a method for realizing it.
摘要翻译：描述了纳米组件的托管结构，其有利地包括：衬底; 所述衬底上具有n≥2的n个阵列电平在生长和平行平面上连续布置，每个平面包括多个导电间隔物，其与多个绝缘间隔物交替并且基本上垂直于所述衬底，并且在至少间隙，位于不同平行平面上的连续阵列电平的导电间隔物，所述不同阵列电平的所述间隙沿着基本上垂直于所述衬底的方向至少部分地对准，定义了沿着所述方向延伸的多个横向主持座，并且适合用于托管至少一个纳米元件。还描述了一种纳米电子设备，其包括这样的托管结构和用于实现它的方法。

7. 发明申请

US20090020747A1 METHOD FOR REALIZING A HOSTING STRUCTURE OF NANOMETRIC ELEMENTS 有权
标题翻译：实现纳米元素的主体结构的方法
公开(公告)号：US20090020747A1
公开(公告)日：2009-01-22
申请号：US12204688
申请日：2008-09-04
申请人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
发明人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
IPC分类号： H01L29/06 , H01L23/48
CPC分类号： H01L21/0337 , H01L21/0338 , Y10S977/70 , Y10S977/701
摘要： A nanometric device comprising a substrate; a plurality of conductive spacers of a conductive material, each conductive spacer being arranged on top of and transverse to the substrate, the conductive spacers including respective pairs of conductive spacers defining respective hosting seats each of less than 30 nm wide; and a plurality of nanometric elements respectively accommodated in the hosting seats.
摘要翻译：一种纳米装置，包括基底; 导电材料的多个导电间隔物，每个导电间隔物布置在衬底的顶部并横向于衬底，导电间隔物包括相应的一对导电间隔物，每个导电间隔物限定各自的托架座位，每个主体座椅的宽度小于30nm; 以及分别容纳在托管座椅中的多个纳米元件。

8. 发明授权

US07456508B2 Hosting structure of nanometric elements and corresponding manufacturing method 有权
标题翻译：纳米元素的主机结构及相应的制造方法
公开(公告)号：US07456508B2
公开(公告)日：2008-11-25
申请号：US11215348
申请日：2005-08-30
申请人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
发明人： Danilo Mascolo , Gianfranco Cerofolini , Gianguido Rizzotto
IPC分类号： H01L27/10
CPC分类号： H01L51/0021 , G11C2213/77 , H01L27/285 , H01L51/0595 , Y10S257/90 , Y10S977/712 , Y10S977/72 , Y10S977/722 , Y10S977/723
摘要： A hosting structure of nanometric components is described comprising a substrate, a first multi-spacer level comprising a first plurality of spacers including first conductive spacers parallel to each other, and at least a second multi-spacer level realized above said first multi-spacer level and comprising a second plurality of spacers arranged transversally to said first plurality of spacers and including at least a lower discontinuous insulating layer and an upper layer, including in turn second conductive spacers. In particular, each pair of spacers of the second multi-spacer level defines with a spacer of the first multi-spacer level a plurality of nanometric hosting seats having at least a first and a second conduction terminal realized by portions of the first conductive spacers and of the second conductive spacers faced in the hosting seats. A method for manufacturing such a structure is also described.
摘要翻译：描述了纳米级元件的托管结构，其包括衬底，第一多间隔物层，包括第一多个间隔物，其包括彼此平行的第一导电间隔物，以及在所述第一多间隔物层上方实现的至少第二多间隔物水平并且包括横向于所述第一多个间隔件布置的第二多个间隔件，并且至少包括下部不连续绝缘层和上层，其又包括第二导电间隔件。特别地，第二多间隔物级别的每对间隔物限定第一多间隔物层的间隔物，多个纳米托管座具有至少第一和第二导电端子，该第一和第二导电端子由第一导电间隔物的部分实现，的第二导电隔离物面向主机座。还描述了制造这种结构的方法。

9. 发明申请

US20090154223A1 METHOD AND DEVICE FOR DEMULTIPLEXING A CROSSBAR NON-VOLATILE MEMORY 有权
标题翻译：用于分解十字架非易失性存储器的方法和装置
公开(公告)号：US20090154223A1
公开(公告)日：2009-06-18
申请号：US12355631
申请日：2009-01-16
申请人： Danilo Mascolo , Gianfranco Cerofolini
发明人： Danilo Mascolo , Gianfranco Cerofolini
IPC分类号： G11C11/00 , H01S4/00
CPC分类号： G11C8/10 , B82Y10/00 , G11C13/0023 , G11C2213/77 , G11C2213/81 , Y10S977/938 , Y10T29/49002
摘要： A method and device demultiplex a crossbar non-volatile memory that includes a first array of row nano-wires and a second array of column nano-wires, which cross the row nano-wires at a plurality of cross-points, hosting plural memory cells. A first electrode and a second electrode respectively cross a modulated doping portion of the row nano-wires and a modulated doping portion of the column nano-wires. A first contact and a second contact respectively the row nano-wires and the column nano-wires. The first electrode and the second electrode are biased respectively with a first and a second adjustable voltage value that progressively switch one by one said memory cells from the OFF state to the ON state, and this state can be memorized.
摘要翻译：一种交叉开关非易失性存储器的方法和装置，其包括行纳米线的第一阵列和列纳米线的第二阵列，其在多个交叉点处跨越所述行纳米线，承载多个存储单元。第一电极和第二电极分别交叉行纳米线的调制掺杂部分和柱纳米线的调制掺杂部分。第一接触和第二接触分别为行纳米线和列纳米线。分别以第一和第二可调电压值偏置第一电极和第二电极，该第一和第二可调电压值逐个地逐个地将所述存储器单元从OFF状态切换到ON状态，并且可以记住该状态。

10. 发明申请

US20080174024A1 METHOD FOR REALIZING AN ELECTRIC LINKAGE IN A SEMICONDUCTOR ELECTRONIC DEVICE BETWEEN A NANOMETRIC CIRCUIT ARCHITECTURE AND STANDARD ELECTRONIC COMPONENTS 有权
标题翻译：在纳米电路结构和标准电子元件之间的半导体电子器件中实现电连接的方法
公开(公告)号：US20080174024A1
公开(公告)日：2008-07-24
申请号：US11971147
申请日：2008-01-08
申请人： Danilo Mascolo , Gianfranco Cerofolini
发明人： Danilo Mascolo , Gianfranco Cerofolini
IPC分类号： H01L23/52 , H01L21/4763
CPC分类号： H01L21/76838 , B82B3/00 , B82Y10/00 , B82Y30/00 , B82Y40/00 , G11C2213/81 , H01L21/76816 , H01L2221/1094 , H01L2924/0002 , H01L2924/00
摘要： A method for realizes electric connections in a semiconductor electronic device between a nanometric circuit architecture and standard electronic components. The method includes: providing a nanometric circuit architecture comprising a succession of conductive nanowires substantially parallel to each other and extended along a direction x; realizing, above the succession, an insulating layer; opening, in the insulating layer, a window of nanometric width b extended along a direction inclined by an angle α with respect to the direction x to substantially cross the whole succession of nanowires, with exposure of a succession of exposed portions of the nanowires, one for each nanowire; realizing, above the insulating layer, a plurality of conductive dies extended along a direction y substantially orthogonal to the direction x and addressed towards the standard electronic components, each of such dies overlapping said window onto a respective exposed portion of a nanowire with obtainment of a plurality of contacts realizing said electric connections.
摘要翻译：一种用于在纳米电路结构和标准电子部件之间实现半导体电子器件中的电连接的方法。该方法包括：提供纳米级电路架构，其包括基本上彼此平行并沿着x方向延伸的一系列导电纳米线; 在继承之上实现绝缘层; 在绝缘层中打开沿着相对于方向x倾斜角度α的方向延伸的纳米宽度b的窗口，以基本上穿过整个纳米线序列，暴露出一连串的纳米线的暴露部分，一个对于每个纳米线; 在绝缘层之上实现沿着基本上正交于方向x的方向y延伸并且朝向标准电子部件寻址的多个导电模具，每个这样的模具将所述窗口重叠到纳米线的相应的暴露部分上，获得一个多个触点实现所述电连接。

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