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1. 发明授权

US06949455B2 Method for forming a semiconductor device structure a semiconductor layer 失效
标题翻译：半导体器件形成半导体层结构的方法
公开(公告)号：US06949455B2
公开(公告)日：2005-09-27
申请号：US10677070
申请日：2003-10-01
申请人： Daniel Thanh-Khac Pham , Bich-Yen Nguyen , James K. Schaeffer , Melissa O. Zavala , Sherry G. Straub , Kimberly G. Reid , Marc Rossow , James P. Geren
发明人： Daniel Thanh-Khac Pham , Bich-Yen Nguyen , James K. Schaeffer , Melissa O. Zavala , Sherry G. Straub , Kimberly G. Reid , Marc Rossow , James P. Geren
IPC分类号： H01L21/28 , H01L21/8238 , H01L29/49 , H01L29/51 , H01L21/3205
CPC分类号： H01L29/517 , H01L21/28061 , H01L21/823835 , H01L21/823842 , H01L21/823857 , H01L29/4933 , H01L29/51
摘要： A method for providing gates of transistors with at least two different work functions utilizes a silicidation of two different metals at different times, silicidation for one gate and polysilicon for the other, or silicidation using a single metal with two differently doped silicon structures. Thus the problem associated with performing silicidation of two different metals at the same time is avoided. If the two metals have significantly different silicidation temperatures, the one with the lower temperature silicidation will likely have significantly degraded performance as a result of having to also experience the higher temperature required to achieve silicidation with the other metal.
摘要翻译：用于提供具有至少两种不同功函数的晶体管栅极的方法利用两种不同金属在不同时间的硅化，一个栅极的硅化，另一个的硅化，或使用具有两个不同掺杂硅结构的单一金属的硅化。因此，避免了与同时进行两种不同金属的硅化相关的问题。如果两种金属具有明显不同的硅化物温度，则由于必须也经历用其它金属进行硅化所需的较高温度，具有较低温度硅化的温度可能会显着降低性能。

2. 发明授权

US07575968B2 Inverse slope isolation and dual surface orientation integration 有权
标题翻译：反斜坡隔离和双面取向积分
公开(公告)号：US07575968B2
公开(公告)日：2009-08-18
申请号：US11742081
申请日：2007-04-30
申请人： Mariam G. Sadaka , Debby Eades , Joe Mogab , Bich-Yen Nguyen , Melissa O. Zavala , Gregory S. Spencer
发明人： Mariam G. Sadaka , Debby Eades , Joe Mogab , Bich-Yen Nguyen , Melissa O. Zavala , Gregory S. Spencer
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807
摘要： A semiconductor process and apparatus provide a high performance CMOS devices (108, 109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse slope isolation techniques to form tapered isolation regions (76) and expose underlying semiconductor layers (41, 42) in a bulk wafer structure prior to epitaxially growing the first and second substrates (84, 82) having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes (104) over a first substrate (84) that is formed by epitaxially growing (100) silicon and forming second gate electrodes (103) over a second substrate (82) that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.
摘要翻译：半导体工艺和装置通过使用反斜率分离技术蚀刻沉积的氧化物层（62）来形成具有混合或双衬底的高性能CMOS器件（108,109），以形成锥形隔离区域（76）并暴露下面的半导体层，42）在外延生长具有不同表面取向的第一和第二衬底（84,82）之前的体晶片结构中，其可以用单个CMP工艺进行平面化。通过在通过外延生长（100）硅并在第二衬底（82）上形成第二栅极（103）形成的第一衬底（84）上形成第一栅电极（104），所述第二衬底（82）通过外延生长（110）硅，获得了包括具有改善的空穴迁移率的高k金属PMOS栅电极的高性能CMOS器件。

3. 发明授权

US07821067B2 Electronic devices including a semiconductor layer 有权
标题翻译：包括半导体层的电子器件
公开(公告)号：US07821067B2
公开(公告)日：2010-10-26
申请号：US11836844
申请日：2007-08-10
申请人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
发明人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/1203
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
摘要翻译：电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。

4. 发明申请

US20080268587A1 Inverse slope isolation and dual surface orientation integration 有权
标题翻译：反斜坡隔离和双面取向积分
公开(公告)号：US20080268587A1
公开(公告)日：2008-10-30
申请号：US11742081
申请日：2007-04-30
申请人： Mariam G. Sadaka , Debby Eades , Joe Mogab , Bich-Yen Nguyen , Melissa O. Zavala , Gregory S. Spencer
发明人： Mariam G. Sadaka , Debby Eades , Joe Mogab , Bich-Yen Nguyen , Melissa O. Zavala , Gregory S. Spencer
IPC分类号： H01L21/8238
CPC分类号： H01L21/823807
摘要： A semiconductor process and apparatus provide a high performance CMOS devices (108, 109) with hybrid or dual substrates by etching a deposited oxide layer (62) using inverse slope isolation techniques to form tapered isolation regions (76) and expose underlying semiconductor layers (41, 42) in a bulk wafer structure prior to epitaxially growing the first and second substrates (84, 82) having different surface orientations that may be planarized with a single CMP process. By forming first gate electrodes (104) over a first substrate (84) that is formed by epitaxially growing (100) silicon and forming second gate electrodes (103) over a second substrate (82) that is formed by epitaxially growing (110) silicon, a high performance CMOS device is obtained which includes high-k metal PMOS gate electrodes having improved hole mobility.
摘要翻译：半导体工艺和装置通过使用反斜率分离技术蚀刻沉积的氧化物层（62）来形成具有混合或双衬底的高性能CMOS器件（108,109），以形成锥形隔离区域（76）并暴露下面的半导体层，42）在外延生长具有不同表面取向的第一和第二衬底（84,82）之前的体晶片结构中，其可以用单个CMP工艺进行平面化。通过在通过外延生长（100）硅并在第二衬底（82）上形成第二栅极（103）形成的第一衬底（84）上形成第一栅电极（104），所述第二衬底（82）通过外延生长（110）硅，获得了包括具有改善的空穴迁移率的高k金属PMOS栅电极的高性能CMOS器件。

5. 发明授权

US07265004B2 Electronic devices including a semiconductor layer and a process for forming the same 有权
标题翻译：包括半导体层的电子器件及其形成方法
公开(公告)号：US07265004B2
公开(公告)日：2007-09-04
申请号：US11273092
申请日：2005-11-14
申请人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
发明人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
IPC分类号： H01L21/84
CPC分类号： H01L21/84 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823878 , H01L27/1203
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.
摘要翻译：电子设备可以包括第一半导体部分和第二半导体部分，其中第一半导体部分和第二半导体部分的组成彼此不同。在一个实施例中，第一和第二半导体部分可以具有彼此不同的应力。在一个实施例中，可以通过在第一半导体部分上形成氧化掩模来形成电子器件。可以在第一半导体层的第二半导体部分上形成第二半导体层，并且与第一半导体层相比具有不同的组成。可以进行氧化，并且可以增加第一半导体层的第二部分内的半导体元素（例如锗）的浓度。在另一个实施例中，可以执行选择性冷凝，并且可以在第一半导体层的第一和第二部分之间形成场隔离区。

6. 发明授权

US07737496B2 Electronic devices including a semiconductor layer 有权
公开(公告)号：US07737496B2
公开(公告)日：2010-06-15
申请号：US11836844
申请日：2007-08-10
申请人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
发明人： Voon-Yew Thean , Brian J. Goolsby , Linda B. McCormick , Bich-Yen Nguyen , Colita M. Parker , Mariam G. Sadaka , Victor H. Vartanian , Ted R. White , Melissa O. Zavala
IPC分类号： H01L21/84
摘要： An electronic device can include a first semiconductor portion and a second semiconductor portion, wherein the compositions of the first and second semiconductor portions are different from each other. In one embodiment, the first and second semiconductor portions can have different stresses compared to each other. In one embodiment, the electronic device may be formed by forming an oxidation mask over the first semiconductor portion. A second semiconductor layer can be formed over the second semiconductor portion of the first semiconductor layer and have a different composition compared to the first semiconductor layer. An oxidation can be performed, and a concentration of a semiconductor element (e.g., germanium) within the second portion of the first semiconductor layer can be increased. In another embodiment, a selective condensation may be performed, and a field isolation region can be formed between the first and second portions of the first semiconductor layer.

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