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1. 发明申请

US20110200051A1 ETHERNET NETWORK SYNCHRONIZATION SYSTEMS AND METHODS 有权
标题翻译：以太网网络同步系统和方法
公开(公告)号：US20110200051A1
公开(公告)日：2011-08-18
申请号：US12706724
申请日：2010-02-17
申请人： Daniel Rivaud , Michael Gazier , Michael Dziawa
发明人： Daniel Rivaud , Michael Gazier , Michael Dziawa
IPC分类号： H04L12/56 , H04J3/06
CPC分类号： H04J3/0641 , H04J3/0644 , H04J3/0658 , H04J3/0667 , H04J3/0673 , H04L12/413
摘要： The present disclosure relates to Ethernet synchronization systems and methods that combines Synchronous Ethernet (Sync-E) and Precision Time Protocol (PTP) IEEE 1588 algorithms. The present invention includes systems and methods for Ethernet networks and node configurations that include a set of rules on node placement, such as Boundary Clock (BC) nodes and Sync-E nodes, a clock selection algorithm, a holdover algorithm, and the like. Advantageously, the present invention provides an architecture that allows practical and real-world useful clock propagation through placement of BCs and Sync-E nodes for best performance. Practical experience and theoretical design are embodied in the present invention to define a very specific set of rules on how to build a network capable of providing accurate and reliable synchronization. The present invention includes clock selection that unifies Sync-E and 1588 algorithms.
摘要翻译：本公开涉及组合了同步以太网（Sync-E）和精确时间协议（PTP）IEEE 1588算法的以太网同步系统和方法。本发明包括用于以太网网络和节点配置的系统和方法，其包括诸如边界时钟（BC）节点和Sync-E节点之类的节点布置的一组规则，时钟选择算法，保持算法等。有利地，本发明提供了一种架构，其通过布置BC和Sync-E节点来实现实际的和现实的有用时钟传播，以获得最佳性能。实践经验和理论设计体现在本发明中以定义关于如何构建能够提供准确和可靠的同步的网络的非常具体的一组规则。本发明包括统一Sync-E和1588算法的时钟选择。

2. 发明授权

US08630315B2 Ethernet network synchronization systems and methods 有权
标题翻译：以太网同步系统和方法
公开(公告)号：US08630315B2
公开(公告)日：2014-01-14
申请号：US12706724
申请日：2010-02-17
申请人： Daniel Rivaud , Michaël Gazier , Michael Dziawa
发明人： Daniel Rivaud , Michaël Gazier , Michael Dziawa
IPC分类号： H04J3/06
CPC分类号： H04J3/0641 , H04J3/0644 , H04J3/0658 , H04J3/0667 , H04J3/0673 , H04L12/413
摘要： The present disclosure relates to Ethernet synchronization systems and methods that combines Synchronous Ethernet (Sync-E) and Precision Time Protocol (PTP) IEEE 1588 algorithms. The present invention includes systems and methods for Ethernet networks and node configurations that include a set of rules on node placement, such as Boundary Clock (BC) nodes and Sync-E nodes, a clock selection algorithm, a holdover algorithm, and the like. Advantageously, the present invention provides an architecture that allows practical and real-world useful clock propagation through placement of BCs and Sync-E nodes for best performance. Practical experience and theoretical design are embodied in the present invention to define a very specific set of rules on how to build a network capable of providing accurate and reliable synchronization. The present invention includes clock selection that unifies Sync-E and 1588 algorithms.
摘要翻译：本公开涉及组合了同步以太网（Sync-E）和精确时间协议（PTP）IEEE 1588算法的以太网同步系统和方法。本发明包括用于以太网网络和节点配置的系统和方法，其包括诸如边界时钟（BC）节点和Sync-E节点之类的节点布置的一组规则，时钟选择算法，保持算法等。有利地，本发明提供了一种架构，其通过布置BC和Sync-E节点来实现实际的和现实的有用时钟传播，以获得最佳性能。实践经验和理论设计体现在本发明中以定义关于如何构建能够提供准确和可靠的同步的网络的非常具体的一组规则。本发明包括统一Sync-E和1588算法的时钟选择。

3. 发明授权

US07181545B2 Network synchronization architecture for a Broadband Loop Carrier (BLC) system 有权
标题翻译：用于宽带环路载波（BLC）系统的网络同步架构
公开(公告)号：US07181545B2
公开(公告)日：2007-02-20
申请号：US10356336
申请日：2003-01-31
申请人： Michael Dziawa , Michael Gazier
发明人： Michael Dziawa , Michael Gazier
IPC分类号： G06F15/16
CPC分类号： H04J3/0688 , H01M8/02
摘要： A combined wide area network (WAN) port/synchronization unit that receives inputs including data and timing information and that synchronizes the data for transmission. The unit includes the following components. A network interface receives the input and removes data and primary timing information from the input. A data-path function processes the data. A reference selection unit receives timing information from the network interface as well as timing information from a secondary combined WAN port/synchronization unit. A synchronization control unit selects the most reliable timing information from the plurality of timing information inputs to the reference selection unit. A multiplexor multiplexes the timing information with the processed data across a link.
摘要翻译：一种组合广域网（WAN）端口/同步单元，其接收包括数据和定时信息的输入，并且将数据同步以进行传输。该单元包括以下组件。网络接口接收输入并从输入中移除数据和主定时信息。数据路径功能处理数据。参考选择单元从网络接口接收定时信息以及来自辅助组合WAN端口/同步单元的定时信息。同步控制单元从参考选择单元的多个定时信息输入中选择最可靠的定时信息。多路复用器通过链路将定时信息与经处理的数据进行多路复用。

4. 发明授权

US07801256B2 Method and apparatus to cancel interference over a group of signals 有权
标题翻译：消除一组信号上的干扰的方法和装置
公开(公告)号：US07801256B2
公开(公告)日：2010-09-21
申请号：US11450341
申请日：2006-06-12
申请人： Michael Wingrove , Michael Dziawa , Ian Dublin
发明人： Michael Wingrove , Michael Dziawa , Ian Dublin
IPC分类号： H03D1/06
CPC分类号： H04B3/32
摘要： A system and method for canceling interference over a group of signals. One or more wires in a group of wires are designated to carry one or more reference signals. The one or more reference signals are used to cancel interference from the data carrying signals in the group of signals. Preferably, the one or more reference signals are subtracted from the data carrying signals to cancel interference from the data carrying signals. Analog or digital elements can be used to subtract the one or more reference signals from the data carrying signals. For example, an operation amplifier or a DSP may be used to perform the subtraction. Filters may be used to further adapt the one or more reference signals prior to the subtracting step to optimize interference cancellation. The filters may be either digital or analog.
摘要翻译：一种用于消除一组信号上的干扰的系统和方法。一组导线中的一根或多根导线被指定为携带一个或多个参考信号。一个或多个参考信号用于消除信号组中的数据携带信号的干扰。优选地，从携带数据的信号中减去一个或多个参考信号以消除数据携带信号的干扰。可以使用模拟或数字元件从数据传送信号中减去一个或多个参考信号。例如，可以使用运算放大器或DSP来执行减法。滤波器可以用于在减法步骤之前进一步调整一个或多个参考信号以优化干扰消除。滤波器可以是数字或模拟的。

5. 发明申请

US20070286295A1 Method and apparatus to cancel interference over a group of signals 有权
标题翻译：消除一组信号上的干扰的方法和装置
公开(公告)号：US20070286295A1
公开(公告)日：2007-12-13
申请号：US11450341
申请日：2006-06-12
申请人： Michael Wingrove , Michael Dziawa , Ian Dublin
发明人： Michael Wingrove , Michael Dziawa , Ian Dublin
IPC分类号： H04B3/00
CPC分类号： H04B3/32
摘要： A system and method for canceling interference over a group of signals. One or more wires in a group of wires are designated to carry one or more reference signals. The one or more reference signals are used to cancel interference from the data carrying signals in the group of signals. Preferably, the one or more reference signals are subtracted from the data carrying signals to cancel interference from the data carrying signals. Analog or digital elements can be used to subtract the one or more reference signals from the data carrying signals. For example, an operation amplifier or a DSP may be used to perform the subtraction. Filters may be used to further adapt the one or more reference signals prior to the subtracting step to optimize interference cancellation. The filters may be either digital or analog.
摘要翻译：一种用于消除一组信号上的干扰的系统和方法。一组导线中的一根或多根导线被指定为携带一个或多个参考信号。一个或多个参考信号用于消除信号组中的数据携带信号的干扰。优选地，从数据携带信号中减去一个或多个参考信号以消除数据携带信号的干扰。可以使用模拟或数字元件从数据传送信号中减去一个或多个参考信号。例如，可以使用运算放大器或DSP来执行减法。滤波器可以用于在减法步骤之前进一步调整一个或多个参考信号以优化干扰消除。滤波器可以是数字或模拟的。

6. 发明授权

US06920217B2 Method and apparatus for transient suppression in an integrated POTS/DSL line card 有权
标题翻译：集成POTS / DSL线路卡中瞬态抑制的方法和装置
公开(公告)号：US06920217B2
公开(公告)日：2005-07-19
申请号：US10278755
申请日：2002-10-22
申请人： Michael Dziawa , Scott McClennon , Francois Tremblay , S. Donald McGinn
发明人： Michael Dziawa , Scott McClennon , Francois Tremblay , S. Donald McGinn
IPC分类号： H04L27/00 , H04L27/26 , H04M11/06
CPC分类号： H04M11/062 , H04L27/0002 , H04L27/2601
摘要： Combined plain old telephone system (POTS) and digital subscriber loop (DSL) line card capable of suppressing low frequency transients. The line card includes the following elements. A DSL receive path receives DSL data from a loop. A POTS receive path receives POTS data from the loop. A combined POTS and DSL transmit path transmits POTS and DSL data to the loop. An impedance generator is coupled between the POTS receive path and the combined POTS and DSL transmit path for synthesizing impedance for signals in the combined POTS and DSL transmit path. A low frequency detector selectively applies a high pass filter to an output of the impedance generator for filtering the low frequency transients. Further, a clipped signal detector and a variable pole high pass filter are provided in the POTS receive path. The clipped signal detector in the POTS receive path triggers a switch that discharges stored transient energy in the receive path. The variable pole high pass filter in the POTS receive path is modified during ringing and hook switch activity, by the line card controller, in order to attenuate transient signals.
摘要翻译：组合普通老式电话系统（POTS）和数字用户回路（DSL）线卡，能够抑制低频瞬变。线卡包括以下元素。 DSL接收路径从循环接收DSL数据。 POTS接收路径从循环接收POTS数据。组合的POTS和DSL传输路径将POTS和DSL数据传输到环路。阻抗发生器耦合在POTS接收路径和用于合成POTS和DSL发送路径中的信号的阻抗的组合的POTS和DSL发送路径之间。低频检测器选择性地向阻抗发生器的输出端施加高通滤波器以对低频瞬变进行滤波。此外，在POTS接收路径中设置有限幅信号检测器和可变杆高通滤波器。 POTS接收路径中的限幅信号检测器触发释放接收路径中存储的瞬态能量的开关。 POTS接收路径中的可变极点高通滤波器在振铃和挂机开关动作期间被线路卡控制器修改，以便衰减瞬态信号。

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