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    • 7. 发明授权
    • Hiding memory latency
    • 隐藏内存延迟
    • US07620951B2
    • 2009-11-17
    • US12049293
    • 2008-03-15
    • Daniel Alan BrokenshireHarm Peter HofsteeBarry L MinorMark Richard Nutter
    • Daniel Alan BrokenshireHarm Peter HofsteeBarry L MinorMark Richard Nutter
    • G06F9/46
    • G06F9/322G06F8/41G06F9/3851
    • An approach to hiding memory latency in a multi-thread environment is presented. Branch Indirect and Set Link (BISL) and/or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code during compilation at instances that correspond to a prolonged instruction. A prolonged instruction is an instruction that instigates latency in a computer system, such as a DMA instruction. When a first thread encounters a BISL or a BISLED instruction, the first thread passes control to a second thread while the first thread's prolonged instruction executes. In turn, the computer system masks the latency of the first thread's prolonged instruction. The system can be optimized based on the memory latency by creating more threads and further dividing a register pool amongst the threads to further hide memory latency in operations that are highly memory bound.
    • 介绍了一种在多线程环境中隐藏内存延迟的方法。 分支间接和设置链接(BISL)和/或分支间接和设置链接,如果外部数据(BISLED)指令在对应于延长的指令的实例的编译期间被放置在线程代码中。 延长的指令是指示计算机系统中的延迟,例如DMA指令。 当第一个线程遇到BISL或BISLED指令时,第一个线程在第一个线程的延长指令执行时将控制传递给第二个线程。 反过来,计算机系统掩盖了第一个线程延长的指令的延迟。 可以通过创建更多线程并在线程之间进一步划分寄存器池来进一步隐藏高度内存限制的操作中的内存延迟,从而可以基于内存延迟来优化系统。
    • 9. 发明授权
    • Dynamically partitioning processing across a plurality of heterogeneous processors
    • 跨多个异构处理器的动态分区处理
    • US08091078B2
    • 2012-01-03
    • US12116628
    • 2008-05-07
    • Daniel Alan BrokenshireHarm Peter HofsteeBarry L MinorMark Richard Nutter
    • Daniel Alan BrokenshireHarm Peter HofsteeBarry L MinorMark Richard Nutter
    • G06F9/45
    • G06F9/4862G06F15/16H04L29/06027H04L63/168H04L67/10H04L67/34
    • A program is into at least two object files: one object file for each of the supported processor environments. During compilation, code characteristics, such as data locality, computational intensity, and data parallelism, are analyzed and recorded in the object file. During run time, the code characteristics are combined with runtime considerations, such as the current load on the processors and the size of the data being processed, to arrive at an overall value. The overall value is then used to determine which of the processors will be assigned the task. The values are assigned based on the characteristics of the various processors. For example, if one processor is better at handling intensive computations against large streams of data, programs that are highly computationally intensive and process large quantities of data are weighted in favor of that processor. The corresponding object is then loaded and executed on the assigned processor.
    • 一个程序进入至少两个对象文件:一个对象文件,用于每个受支持的处理器环境。 在编译过程中,将数据位置,计算强度和数据并行等代码特征分析并记录在目标文件中。 在运行时间期间,代码特征与运行时考虑相结合,例如处理器上的当前负载和正在处理的数据的大小,以达到总体值。 然后,总体值用于确定哪些处理器将被分配任务。 这些值基于各种处理器的特性分配。 例如,如果一个处理器更好地处理针对大量数据流的密集计算,则高度计算密集的程序和处理大量数据的程序对该处理器进行加权。 然后在分配的处理器上加载和执行相应的对象。
    • 10. 发明申请
    • Hiding Memory Latency
    • 隐藏内存延迟
    • US20080162906A1
    • 2008-07-03
    • US12049293
    • 2008-03-15
    • Daniel Alan BrokenshireHarm Peter HofsteeBarry L MinorMark Richard Nutter
    • Daniel Alan BrokenshireHarm Peter HofsteeBarry L MinorMark Richard Nutter
    • G06F9/30
    • G06F9/322G06F8/41G06F9/3851
    • An approach to hiding memory latency in a multi-thread environment is presented. Branch Indirect and Set Link (BISL) and/or Branch Indirect and Set Link if External Data (BISLED) instructions are placed in thread code during compilation at instances that correspond to a prolonged instruction. A prolonged instruction is an instruction that instigates latency in a computer system, such as a DMA instruction. When a first thread encounters a BISL or a BISLED instruction, the first thread passes control to a second thread while the first thread's prolonged instruction executes. In turn, the computer system masks the latency of the first thread's prolonged instruction. The system can be optimized based on the memory latency by creating more threads and further dividing a register pool amongst the threads to further hide memory latency in operations that are highly memory bound.
    • 介绍了一种在多线程环境中隐藏内存延迟的方法。 分支间接和设置链接(BISL)和/或分支间接和设置链接,如果外部数据(BISLED)指令在对应于延长的指令的实例的编译期间被放置在线程代码中。 延长的指令是指示计算机系统中的延迟,例如DMA指令。 当第一个线程遇到BISL或BISLED指令时,第一个线程在第一个线程的延长指令执行时将控制传递给第二个线程。 反过来,计算机系统掩盖了第一个线程延长的指令的延迟。 可以通过创建更多线程并在线程之间进一步划分寄存器池来进一步隐藏高度内存限制的操作中的内存延迟,从而基于内存延迟来优化系统。