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1. 发明授权

US07509247B2 Electromagnetic solutions for full-chip analysis 有权
标题翻译：用于全芯片分析的电磁解决方案
公开(公告)号：US07509247B2
公开(公告)日：2009-03-24
申请号：US11098538
申请日：2005-04-05
申请人： Dan Jiao , Changhong Dai
发明人： Dan Jiao , Changhong Dai
IPC分类号： G06F7/60 , G06F17/50 , G06F9/45
CPC分类号： G06F7/60 , G06F17/5018 , G06F2217/16
摘要： A modeling method is provided that includes receiving a computational model of a structure and slicing the computational model into a plurality of circuit prints. The plurality of slices may include essential circuit prints and backfill circuit prints. Various unknowns may be eliminated between essential circuit prints of the computational model. The unknowns to be eliminated may include volume unknowns and backfill circuit-print unknowns. The numerical system formed by circuit-print unknowns may be divided into a plurality of blocks. The blocks may be solved in turn. One block may be solved by projecting the contributions from other blocks to this block. The solution of the one block may be translated to other blocks to solve unknowns therein. The computational model may then be solved to determine electromagnetic and circuit characteristics of the structure.
摘要翻译：提供了一种建模方法，其包括接收结构的计算模型并将所述计算模型切片成多个电路印刷。多个切片可以包括必要的电路印刷和回填电路印刷。在计算模型的基本电路图之间可以消除各种未知数。要消除的未知数可能包括体积未知数和回填电路印刷未知数。由电路打印未知数形成的数值系统可以被分成多个块。块可以依次解决。可以通过将来自其他块的贡献投影到该块来解决一个块。一个块的解可以转换成其他块来解决其中的未知数。然后可以解决计算模型以确定结构的电磁和电路特性。

2. 发明授权

US07289945B2 Analyzing interconnect structures 有权
标题翻译：分析互连结构
公开(公告)号：US07289945B2
公开(公告)日：2007-10-30
申请号：US10281857
申请日：2002-10-28
申请人： Dan Jiao , Mohiuddin Mazumder , Changhong Dai
发明人： Dan Jiao , Mohiuddin Mazumder , Changhong Dai
IPC分类号： G06F17/50
CPC分类号： G06F17/5036 , G06F17/5018
摘要： In one embodiment, an interconnect structure may be analyzed to determine electromagnetic characteristics of the structure by identifying structure seeds corresponding to the structure; modeling the structure seeds to obtain field patterns; and processing the field patterns to obtain the electromagnetic characteristics.
摘要翻译：在一个实施例中，可以分析互连结构以通过识别对应于该结构的结构种子来确定结构的电磁特性; 模拟结构种子以获得场模式; 并处理场模式以获得电磁特性。

3. 发明申请

US20060224373A1 Electromagnetic solutions for full-chip analysis 有权
公开(公告)号：US20060224373A1
公开(公告)日：2006-10-05
申请号：US11098538
申请日：2005-04-05
申请人： Dan Jiao , Changhong Dai
发明人： Dan Jiao , Changhong Dai
IPC分类号： G06F17/50
CPC分类号： G06F7/60 , G06F17/5018 , G06F2217/16
摘要： A modeling method is provided that includes receiving a computational model of a structure and slicing the computational model into a plurality of circuit prints. The plurality of slices may include essential circuit prints and backfill circuit prints. Various unknowns may be eliminated between essential circuit prints of the computational model. The unknowns to be eliminated may include volume unknowns and backfill circuit-print unknowns. The numerical system formed by circuit-print unknowns may be divided into a plurality of blocks. The blocks may be solved in turn. One block may be solved by projecting the contributions from other blocks to this block. The solution of the one block may be translated to other blocks to solve unknowns therein. The computational model may then be solved to determine electromagnetic and circuit characteristics of the structure.

4. 发明申请

US20070013023A1 Isolation structure configurations for modifying stresses in semiconductor devices 审中-公开
标题翻译：用于修改半导体器件中的应力的隔离结构配置
公开(公告)号：US20070013023A1
公开(公告)日：2007-01-18
申请号：US11525982
申请日：2006-09-22
申请人： Qing Ma , Jin Lee , Harry Fujimoto , Changhong Dai , Shiuh-Wuu Lee , Travis Eiles , Krishna Seshan
发明人： Qing Ma , Jin Lee , Harry Fujimoto , Changhong Dai , Shiuh-Wuu Lee , Travis Eiles , Krishna Seshan
IPC分类号： H01L29/00
CPC分类号： H01L29/7842 , H01L21/76224 , H01L29/7846 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2224/73265 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.
摘要翻译：一种用于修改MOS器件的隔离结构配置以诱导或减小MOS器件的有源区上的拉伸和/或压缩应力的装置和方法。根据本发明的隔离结构构造包括使用低模量和高模量介电材料以及拉伸应力诱导和压应力诱导介电材料，还包括改变隔离深度用于改变隔离结构构造的结构和方法，例如使用的沟槽深度和隔离材料，以修饰（即，诱发或减少）半导体器件的有源区域上的拉伸和/或压缩应力。

5. 发明申请

US20150024151A1 LOW PRESSURE AIR OR VACUUM GLASS EDGE-SEALED WITH BAR FRAME AND GROOVE 审中-公开
标题翻译：低压空气或真空玻璃边缘，密封边框和栅栏
公开(公告)号：US20150024151A1
公开(公告)日：2015-01-22
申请号：US14383702
申请日：2013-03-21
申请人： Changhong Dai
发明人： Changhong Dai
IPC分类号： C03C27/10 , C03B23/025 , E06B3/66
CPC分类号： C03C27/10 , C03C3/091 , C03C8/24 , C03C27/06 , E06B3/6612 , E06B3/66304 , E06B2003/66338 , Y02A30/25 , Y02B80/24
摘要： A low pressure air or vacuum glass and manufacturing method thereof, the low pressure air or vacuum glass comprising upper glass and lower glass; the upper glass and the lower glass are flat glass or convex glass; the peripheries of the upper glass and the lower glass are provided with an edge sealing bar frame and/or an edge sealing groove, and are welded together via a low temperature glass solder, thus forming a closed low pressure air layer or vacuum layer therebetween. The low pressure or vacuum glass is of simple manufacturing process, low cost, high production efficiency, reliable sealing connection, and good sealing effect.
摘要翻译：低压空气或真空玻璃及其制造方法，包括上玻璃和下玻璃的低压空气或真空玻璃; 上玻璃和下玻璃是平玻璃或凸玻璃; 上玻璃和下玻璃的周边设置有边缘密封条框架和/或边缘密封槽，并通过低温玻璃焊料焊接在一起，从而在其间形成封闭的低压空气层或真空层。低压或真空玻璃制造工艺简单，成本低，生产效率高，密封连接可靠，密封效果好。

6. 发明授权

US06876053B1 Isolation structure configurations for modifying stresses in semiconductor devices 有权
标题翻译：用于修改半导体器件应力的隔离结构配置
公开(公告)号：US06876053B1
公开(公告)日：2005-04-05
申请号：US09374502
申请日：1999-08-13
申请人： Qing Ma , Jin Lee , Harry Fujimoto , Changhong Dai , Shiuh-Wuu Lee , Travis Eiles , Krishna Seshan
发明人： Qing Ma , Jin Lee , Harry Fujimoto , Changhong Dai , Shiuh-Wuu Lee , Travis Eiles , Krishna Seshan
IPC分类号： H01L21/762 , H01L29/00 , H01L29/76 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7842 , H01L21/76224 , H01L29/7846 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2224/73265 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.
摘要翻译：一种用于修改MOS器件的隔离结构配置以诱导或减小MOS器件的有源区上的拉伸和/或压缩应力的装置和方法。根据本发明的隔离结构构造包括使用低模量和高模量介电材料以及拉伸应力诱导和压应力诱导介电材料，还包括改变隔离深度用于改变隔离结构构造的结构和方法，例如使用的沟槽深度和隔离材料，以修饰（即，诱发或减少）半导体器件的有源区域上的拉伸和/或压缩应力。

7. 发明申请

US20140107476A1 SPATIAL SAMPLING IMPROVEMENT FOR LIST-MODE PET ACQUISITION USING PLANNED TABLE/GANTRY MOVEMENT 审中-公开
标题翻译：使用计划表/ GANTRY运动的列表模式PET获取的空间抽样改进
公开(公告)号：US20140107476A1
公开(公告)日：2014-04-17
申请号：US14124351
申请日：2012-06-01
申请人： Chi-Hua Tung , Bin Zhang , Changhong Dai
发明人： Chi-Hua Tung , Bin Zhang , Changhong Dai
IPC分类号： A61B6/03
CPC分类号： A61B6/037 , A61B6/04 , A61B6/5205 , A61B6/547 , G01T1/1647
摘要： A PET apparatus includes a detector array including individual detectors which receive radiation events from an imaging region. A movement controller controls at least one of relative longitudinal movement between a subject support and the detector array and circumferential movement between the detector array and the subject. A time stamp processor assigns a time stamp to each received radiation event. A list mode event storage buffer stores time stamped events. An event verification processor screens for coincidentally received radiation events, locations at which each pair of corresponding coincidentally received events defining a line of response. A reconstruction processor reconstructs valid events into an image representation of the imaging region.
摘要翻译： PET装置包括检测器阵列，其包括从成像区域接收辐射事件的各个检测器。运动控制器控制受检者支架和检测器阵列之间的相对纵向移动中的至少一个以及检测器阵列和被检体之间的周向运动。时间戳处理器为每个接收到的辐射事件分配时间戳。列表模式事件存储缓冲区存储时间戳事件。事件验证处理器屏蔽偶然接收的辐射事件，每对对应的巧合接收事件定义响应行的位置。重建处理器将有效事件重建成成像区域的图像表示。

8. 发明授权

US07411269B2 Isolation structure configurations for modifying stresses in semiconductor devices 有权
公开(公告)号：US07411269B2
公开(公告)日：2008-08-12
申请号：US11091967
申请日：2005-03-28
申请人： Qing Ma , Jin Lee , Harry Fujimoto , Changhong Dai , Shiuh-Wuu Lee , Travis Eiles , Krishna Seshan
发明人： Qing Ma , Jin Lee , Harry Fujimoto , Changhong Dai , Shiuh-Wuu Lee , Travis Eiles , Krishna Seshan
IPC分类号： H01L29/72
CPC分类号： H01L29/7842 , H01L21/76224 , H01L29/7846 , H01L2224/16225 , H01L2224/32225 , H01L2224/48091 , H01L2224/73204 , H01L2224/73265 , H01L2924/13091 , H01L2924/00014 , H01L2924/00
摘要： An apparatus and methods for modifying isolation structure configurations for MOS devices to either induce or reduce tensile and/or compressive stresses on an active area of the MOS devices. The isolation structure configurations according to the present invention include the use of low-modulus and high-modulus, dielectric materials, as well as, tensile stress-inducing and compressive stress-inducing, dielectric materials, and further includes altering the depth of the isolation structure and methods for modifying isolation structure configurations, such as trench depth and isolation materials used, to modify (i.e., to either induce or reduce) tensile and/or compressive stresses on an active area of a semiconductor device.

9. 发明申请

US20070005325A1 Circuit simulation using precision-space concept 审中-公开
标题翻译：电路仿真采用精密空间概念
公开(公告)号：US20070005325A1
公开(公告)日：2007-01-04
申请号：US11174124
申请日：2005-06-30
申请人： Jian Gong , Changhong Dai
发明人： Jian Gong , Changhong Dai
IPC分类号： G06F17/50
CPC分类号： G06F17/504
摘要： An arrangement is provided for using a precision space (“p-space”) to represent s-parameters when analyzing/simulating a circuit/network. The p-space is one dimensional with a value range corresponding to the value range of s-parameters. The p-space is divided into multiple slots where the number of slots may depend on the permissible precision of s-parameter values. A mapping relationship between s-parameters and p-space slots may be obtained by partitioning an s-parameter matrix. Based on the mapping relationship, p-space representations of original s-parameters may be generated through a forward projection process from s-parameters in a two-dimensional matrix to the one-dimensional p-space. During the simulation process, a p-space representation may be projected back to original s-parameters in a matrix based on the mapping relationship.
摘要翻译：提供了一种在分析/模拟电路/网络时使用精密空间（“p空间”）表示s参数的布置。 p空间是与s参数的值范围对应的值范围的一维。 p空间被分成多个槽，其中槽数可以取决于s参数值的允许精度。可以通过划分s参数矩阵来获得s参数和p空间时隙之间的映射关系。基于映射关系，可以通过从二维矩阵中的s参数到一维p空间的前向投影处理来生成原始s参数的p空间表示。在仿真过程中，可以基于映射关系将p空间表示投影回矩阵中的原始s参数。

10. 发明申请

US20070005324A1 Method and apparatus for simulating circuits using s-parameters 审中-公开
标题翻译：使用s参数模拟电路的方法和装置
公开(公告)号：US20070005324A1
公开(公告)日：2007-01-04
申请号：US11174071
申请日：2005-06-30
申请人： Jian Gong , Changhong Dai
发明人： Jian Gong , Changhong Dai
IPC分类号： G06F17/50
CPC分类号： G06F17/5036
摘要： An arrangement is provided for using s-parameters to obtain characteristics of a device under test (“DUT”) between a number of selected observation locations. The DUT may be represented by a network of models such as lumped device models and transmission line models. S-parameters between the selected nodes may be measured based on the DUT representation at a plurality of frequency points. The measured s-parameters may be converted into their precision space (“p-space”) representations, which may then be submitted to a simulator to obtain the DUT characteristics at the selected observation nodes.
摘要翻译：提供了一种用于使用s参数来获得多个所选观察位置之间的待测设备（“DUT”）的特性的装置。 DUT可以由诸如集总装置模型和传输线模型的模型网络来表示。可以基于多个频点处的DUT表示来测量所选节点之间的S参数。测量的s参数可以转换成它们的精确空间（“p空间”）表示，然后可以将其提交给模拟器以在所选择的观测节点处获得DUT特性。

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