专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

US20120086065A1 SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有垂直通道晶体管的半导体器件及其制造方法
公开(公告)号：US20120086065A1
公开(公告)日：2012-04-12
申请号：US13097343
申请日：2011-04-29
申请人： Daeik KIM , Yongchul Oh , Yoosang Hwang , Hyun-Woo Chung , Young-Seung Cho
发明人： Daeik KIM , Yongchul Oh , Yoosang Hwang , Hyun-Woo Chung , Young-Seung Cho
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/108 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： Provided is a semiconductor device having a vertical channel transistor and method of fabricating the same. The semiconductor device includes first and second field effect transistors, wherein a channel region of the first field effect transistor serves as source/drain electrodes of the second field effect transistor, and a channel region of the second field effect transistor serves as source/drain electrodes of the first field effect transistor.
摘要翻译：提供一种具有垂直沟道晶体管的半导体器件及其制造方法。半导体器件包括第一和第二场效应晶体管，其中第一场效应晶体管的沟道区用作第二场效应晶体管的源/漏电极，第二场效应晶体管的沟道区用作源极/漏极的第一场效应晶体管。

2. 发明授权

US08384141B2 Semiconductor device with vertical channel transistor 有权
标题翻译：具有垂直沟道晶体管的半导体器件
公开(公告)号：US08384141B2
公开(公告)日：2013-02-26
申请号：US13097343
申请日：2011-04-29
申请人： Daeik Kim , Yongchul Oh , Yoosang Hwang , Hyun-Woo Chung , Young-Seung Cho
发明人： Daeik Kim , Yongchul Oh , Yoosang Hwang , Hyun-Woo Chung , Young-Seung Cho
IPC分类号： H01L27/108 , H01L29/94 , H01L21/336
CPC分类号： H01L27/108 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L29/66666 , H01L29/7827
摘要： Provided is a semiconductor device having a vertical channel transistor and method of fabricating the same. The semiconductor device includes first and second field effect transistors, wherein a channel region of the first field effect transistor serves as source/drain electrodes of the second field effect transistor, and a channel region of the second field effect transistor serves as source/drain electrodes of the first field effect transistor.
摘要翻译：提供一种具有垂直沟道晶体管的半导体器件及其制造方法。半导体器件包括第一和第二场效应晶体管，其中第一场效应晶体管的沟道区用作第二场效应晶体管的源/漏电极，第二场效应晶体管的沟道区用作源极/漏极的第一场效应晶体管。

3. 发明申请

US20130001675A1 SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20130001675A1
公开(公告)日：2013-01-03
申请号：US13533373
申请日：2012-06-26
申请人： Hyun-Woo Chung , Jiyoung Kim , Yongchul Oh , Sungkwan Choi , Yoosang Hwang
发明人： Hyun-Woo Chung , Jiyoung Kim , Yongchul Oh , Sungkwan Choi , Yoosang Hwang
IPC分类号： H01L29/78
CPC分类号： H01L27/10876 , H01L27/10823
摘要： A semiconductor device includes a semiconductor substrate including first trenches defining outer sidewalls of a pair of active pillars and a second trench defining opposing inner sidewalls of the pair of active pillars. The second trench may have a bottom surface located at a higher level than bottom surface of the first trench. Auxiliary conductive lines may be disposed in the first trenches to cover and cross the outer sidewalls of the pair of active pillars. A pair of main conductive lines may be disposed in a pair of recessed regions that are laterally recessed from lower portions of the inner sidewalls of the active pillars into the pair of active pillars. A common impurity region may be disposed in the semiconductor substrate under the second trench. Upper impurity regions may be disposed in upper portions of the active pillars.
摘要翻译：半导体器件包括半导体衬底，其包括限定一对有源柱的外侧壁的第一沟槽和限定该对有源柱的相对内侧壁的第二沟槽。第二沟槽可以具有位于比第一沟槽的底表面更高的水平面的底表面。辅助导线可以设置在第一沟槽中以覆盖并穿过该对活动柱的外侧壁。一对主导线可以设置在从活动柱的内侧壁的下部侧向凹入一对活动柱的一对凹陷区域中。可以在第二沟槽下方的半导体衬底中设置公共杂质区域。上部杂质区域可以设置在活性支柱的上部。

4. 发明授权

US09165935B2 Semiconductor devices and methods for manufacturing the same 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US09165935B2
公开(公告)日：2015-10-20
申请号：US13533373
申请日：2012-06-26
申请人： Hyun-Woo Chung , Jiyoung Kim , Yongchul Oh , Sungkwan Choi , Yoosang Hwang
发明人： Hyun-Woo Chung , Jiyoung Kim , Yongchul Oh , Sungkwan Choi , Yoosang Hwang
IPC分类号： H01L27/108
CPC分类号： H01L27/10876 , H01L27/10823
摘要： A semiconductor device includes a semiconductor substrate including first trenches defining outer sidewalls of a pair of active pillars and a second trench defining opposing inner sidewalls of the pair of active pillars. The second trench may have a bottom surface located at a higher level than bottom surface of the first trench. Auxiliary conductive lines may be disposed in the first trenches to cover and cross the outer sidewalls of the pair of active pillars. A pair of main conductive lines may be disposed in a pair of recessed regions that are laterally recessed from lower portions of the inner sidewalls of the active pillars into the pair of active pillars. A common impurity region may be disposed in the semiconductor substrate under the second trench. Upper impurity regions may be disposed in upper portions of the active pillars.
摘要翻译：半导体器件包括半导体衬底，其包括限定一对有源柱的外侧壁的第一沟槽和限定该对有源柱的相对内侧壁的第二沟槽。第二沟槽可以具有位于比第一沟槽的底表面更高的水平面的底表面。辅助导线可以设置在第一沟槽中以覆盖并穿过该对活动柱的外侧壁。一对主导线可以设置在从活动柱的内侧壁的下部侧向凹入一对活动柱的一对凹陷区域中。可以在第二沟槽下方的半导体衬底中设置公共杂质区域。上部杂质区域可以设置在活性支柱的上部。

5. 发明授权

US08344437B2 Semiconductor device with vertical channel transistor 有权
标题翻译：具有垂直沟道晶体管的半导体器件
公开(公告)号：US08344437B2
公开(公告)日：2013-01-01
申请号：US13097365
申请日：2011-04-29
申请人： Daeik Kim , HyeongSun Hong , Yoosang Hwang , Hyun-Woo Chung
发明人： Daeik Kim , HyeongSun Hong , Yoosang Hwang , Hyun-Woo Chung
IPC分类号： H01L27/108 , H01L29/94 , H01L29/76 , H01L21/331
CPC分类号： H01L27/10844 , H01L27/108 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L29/66666 , H01L29/7827 , H01L29/94
摘要： A semiconductor memory device includes a semiconductor substrate, a semiconductor pillar extending from the semiconductor substrate, the semiconductor pillar comprising a first region, a second region, and a third region, the second region positioned between the first region and the third region, the third region positioned between the second region and the semiconductor substrate, immediately adjacent regions having different conductivity types, a first gate pattern disposed on the second region with a first insulating layer therebetween, and a second gate pattern disposed on the third region, wherein the second region is ohmically connected to the substrate by the second gate pattern.
摘要翻译：半导体存储器件包括半导体衬底，从半导体衬底延伸的半导体柱，所述半导体柱包括第一区域，第二区域和第三区域，所述第二区域位于第一区域和第三区域之间，第三区域位于第二区域和半导体衬底之间的区域，具有不同导电类型的紧邻区域，设置在第二区域上的第一栅极图案，其间具有第一绝缘层，以及设置在第三区域上的第二栅极图案，其中第二区域通过第二栅极图案欧姆连接到衬底。

6. 发明申请

US20130171783A1 METHOD OF FABRICATING SEMICONDUCTOR DEVICE WITH VERTICAL CHANNEL TRANSISTOR 有权
标题翻译：用垂直通道晶体管制作半导体器件的方法
公开(公告)号：US20130171783A1
公开(公告)日：2013-07-04
申请号：US13708534
申请日：2012-12-07
申请人： Daeik Kim , HyeongSun Hong , Yoosang Hwang , Hyun-Woo Chung
发明人： Daeik Kim , HyeongSun Hong , Yoosang Hwang , Hyun-Woo Chung
IPC分类号： H01L27/108
CPC分类号： H01L27/10844 , H01L27/108 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L29/66666 , H01L29/7827 , H01L29/94
摘要： A semiconductor memory device includes a semiconductor substrate, a semiconductor pillar extending from the semiconductor substrate, the semiconductor pillar comprising a first region, a second region, and a third region, the second region positioned between the first region and the third region, the third region positioned between the second region and the semiconductor substrate, immediately adjacent regions having different conductivity types, a first gate pattern disposed on the second region with a first insulating layer therebetween, and a second gate pattern disposed on the third region, wherein the second region is ohmically connected to the substrate by the second gate pattern.
摘要翻译：半导体存储器件包括半导体衬底，从半导体衬底延伸的半导体柱，所述半导体柱包括第一区域，第二区域和第三区域，所述第二区域位于第一区域和第三区域之间，第三区域位于第二区域和半导体衬底之间的区域，具有不同导电类型的紧邻区域，设置在第二区域上的第一栅极图案，其间具有第一绝缘层，以及设置在第三区域上的第二栅极图案，其中第二区域通过第二栅极图案欧姆连接到衬底。

7. 发明授权

US09111960B2 Semiconductor devices with vertical channel transistors 有权
标题翻译：具有垂直沟道晶体管的半导体器件
公开(公告)号：US09111960B2
公开(公告)日：2015-08-18
申请号：US13242660
申请日：2011-09-23
申请人： Hui-Jung Kim , Yongchul Oh , Daeik Kim , Hyun-Woo Chung
发明人： Hui-Jung Kim , Yongchul Oh , Daeik Kim , Hyun-Woo Chung
IPC分类号： H01L29/78 , H01L29/66 , H01L27/108
CPC分类号： H01L29/66666 , H01L27/10876 , H01L29/7827
摘要： Semiconductor devices with vertical channel transistors, the devices including semiconductor patterns disposed on a substrate, first gate patterns disposed between the semiconductor patterns on the substrate, a second gate pattern spaced apart from the first gate patterns by the semiconductor patterns, and conductive lines crossing the first gate patterns. The second gate pattern includes a first portion extending parallel to the first gate patterns and a second portion extending parallel to the conductive lines.
摘要翻译：具有垂直沟道晶体管的半导体器件，包括设置在衬底上的半导体图案的器件，设置在衬底上的半导体图案之间的第一栅极图案，通过半导体图案与第一栅极图案间隔开的第二栅极图案，第一门模式。第二栅极图案包括平行于第一栅极图案延伸的第一部分和平行于导电线延伸的第二部分。

8. 发明授权

US08524560B2 Method of fabricating semiconductor device with vertical channel transistor 有权
标题翻译：制造具有垂直沟道晶体管的半导体器件的方法
公开(公告)号：US08524560B2
公开(公告)日：2013-09-03
申请号：US13708534
申请日：2012-12-07
申请人： Daeik Kim , HyeongSun Hong , Yoosang Hwang , Hyun-Woo Chung
发明人： Daeik Kim , HyeongSun Hong , Yoosang Hwang , Hyun-Woo Chung
IPC分类号： H01L21/336 , H01L21/44
CPC分类号： H01L27/10844 , H01L27/108 , H01L27/10814 , H01L27/10823 , H01L27/10876 , H01L29/66666 , H01L29/7827 , H01L29/94
摘要： A semiconductor memory device includes a semiconductor substrate, a semiconductor pillar extending from the semiconductor substrate, the semiconductor pillar comprising a first region, a second region, and a third region, the second region positioned between the first region and the third region, the third region positioned between the second region and the semiconductor substrate, immediately adjacent regions having different conductivity types, a first gate pattern disposed on the second region with a first insulating layer therebetween, and a second gate pattern disposed on the third region, wherein the second region is ohmically connected to the substrate by the second gate pattern.
摘要翻译：半导体存储器件包括半导体衬底，从半导体衬底延伸的半导体柱，所述半导体柱包括第一区域，第二区域和第三区域，所述第二区域位于第一区域和第三区域之间，第三区域位于第二区域和半导体衬底之间的区域，具有不同导电类型的紧邻区域，设置在第二区域上的第一栅极图案，其间具有第一绝缘层，以及设置在第三区域上的第二栅极图案，其中第二区域通过第二栅极图案欧姆连接到衬底。

9. 发明申请

US20120153379A1 SEMICONDUCTOR DEVICES WITH VERTICAL CHANNEL TRANSISTORS 有权
标题翻译：具有垂直通道晶体管的半导体器件
公开(公告)号：US20120153379A1
公开(公告)日：2012-06-21
申请号：US13242660
申请日：2011-09-23
申请人： Hui-Jung Kim , Yongchul Oh , Daeik Kim , Hyun-Woo Chung
发明人： Hui-Jung Kim , Yongchul Oh , Daeik Kim , Hyun-Woo Chung
IPC分类号： H01L29/78
CPC分类号： H01L29/66666 , H01L27/10876 , H01L29/7827
摘要： Semiconductor devices with vertical channel transistors, the devices including semiconductor patterns disposed on a substrate, first gate patterns disposed between the semiconductor patterns on the substrate, a second gate pattern spaced apart from the first gate patterns by the semiconductor patterns, and conductive lines crossing the first gate patterns. The second gate pattern includes a first portion extending parallel to the first gate patterns and a second portion extending parallel to the conductive lines.
摘要翻译：具有垂直沟道晶体管的半导体器件，包括设置在衬底上的半导体图案的器件，设置在衬底上的半导体图案之间的第一栅极图案，通过半导体图案与第一栅极图案间隔开的第二栅极图案，第一门模式。第二栅极图案包括平行于第一栅极图案延伸的第一部分和平行于导电线延伸的第二部分。

10. 发明授权

US08987111B2 Method of manufacturing a three dimensional array having buried word lines of different heights and widths 有权
标题翻译：制造具有不同高度和宽度的掩埋字线的三维阵列的方法
公开(公告)号：US08987111B2
公开(公告)日：2015-03-24
申请号：US13789930
申请日：2013-03-08
申请人： Jay-Bok Choi , Jiyoung Kim , Hyun-Woo Chung , Sungkwan Choi , Yoosang Hwang
发明人： Jay-Bok Choi , Jiyoung Kim , Hyun-Woo Chung , Sungkwan Choi , Yoosang Hwang
IPC分类号： H01L21/76 , H01L21/762 , H01L21/308 , H01L27/108
CPC分类号： H01L23/5283 , H01L21/3086 , H01L21/76224 , H01L27/10891 , H01L29/0649 , H01L2924/0002 , H01L2924/00
摘要： According to a method of fabricating a semiconductor device, a first mask pattern is used to etch first device isolation layers and active lines or form grooves, in which word lines will be provided. Thereafter, the active lines are etched in a self-alignment manner by using the first mask pattern as an etch mask. As a result, it is possible to suppress mask misalignment from occurring.
摘要翻译：根据制造半导体器件的方法，使用第一掩模图案来蚀刻第一器件隔离层和有源线或形成凹槽，其中将提供字线。此后，通过使用第一掩模图案作为蚀刻掩模，以自对准方式蚀刻有源线。结果，可以抑制掩模未对准的发生。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式