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1. 发明授权

US08253465B2 Semiconductor memory device and method for operating the same 有权
标题翻译：半导体存储器件及其操作方法
公开(公告)号：US08253465B2
公开(公告)日：2012-08-28
申请号：US13186366
申请日：2011-07-19
申请人： Dae-Kun Yoon , Dae-Han Kwon , Taek-Sang Song
发明人： Dae-Kun Yoon , Dae-Han Kwon , Taek-Sang Song
IPC分类号： H03K3/00 , H03K5/13 , H03H11/16
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1072 , G11C7/222 , H03L7/0814
摘要： A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.
摘要翻译：半导体存储器件包括边缘检测器，被配置为接收两对互补时钟以检测时钟的边沿;比较器，被配置为比较边缘检测器的输出信号，以检测同一对的时钟是否具有180度的相位差;以及检测不同对的时钟是否具有90度的相位差，控制信号发生器被配置为根据比较器的输出信号产生用于控制时钟相位的控制信号;以及相位校正器，被配置为校正时钟的相位响应于控制信号。

2. 发明授权

US08570109B2 Ring oscillator for generating oscillating clock signal 有权
标题翻译：用于产生振荡时钟信号的环形振荡器
公开(公告)号：US08570109B2
公开(公告)日：2013-10-29
申请号：US13081119
申请日：2011-04-06
申请人： Taek-Sang Song , Dae-Han Kwon , Dae-Kun Yoon
发明人： Taek-Sang Song , Dae-Han Kwon , Dae-Kun Yoon
IPC分类号： H03K3/03
CPC分类号： H03K3/0322 , H03K23/542
摘要： A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.
摘要翻译：一种环形振荡器，包括多个缓冲单元，每个缓冲单元具有交叉耦合结构，用于使用施加有预定电压电平的偏置电压来产生时钟信号，其中时钟信号具有对应于偏置电压的摆幅宽度。

3. 发明授权

US07812650B2 Bias voltage generation circuit and clock synchronizing circuit 有权
标题翻译：偏置电压发生电路和时钟同步电路
公开(公告)号：US07812650B2
公开(公告)日：2010-10-12
申请号：US12157235
申请日：2008-06-09
申请人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon , Dae-Kun Yoon
发明人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon , Dae-Kun Yoon
IPC分类号： H03L7/06
CPC分类号： H03L7/0893 , H03L7/099 , H03L7/107 , H03L2207/06
摘要： Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.
摘要翻译：偏置电压发生器电路和时钟同步电路包括被配置为响应于带宽控制信号来控制电流的偏置单元，被配置为响应于由偏置单元控制的电流差异放大输入信号的放大单元和配置的输出单元以接收放大单元的输出信号以输出偏置电压。

4. 发明授权

US07791391B2 Quadrature phase correction circuit 有权
标题翻译：正交相位校正电路
公开(公告)号：US07791391B2
公开(公告)日：2010-09-07
申请号：US12215829
申请日：2008-06-30
申请人： Dae-Kun Yoon , Dae-Han Kwon , Taek-Sang Song
发明人： Dae-Kun Yoon , Dae-Han Kwon , Taek-Sang Song
IPC分类号： H03K5/13
CPC分类号： H03L7/0814 , H03K2005/00286 , H03L7/087
摘要： A quadrature phase correction circuit includes an N-bit code counter configured to generate an N-bit code value according to a detected phase difference when a quadrature phase correction is carried out, N-bit code values are stored according to a plurality of detected phase differences. A controller shares the N-bit code counter, controls the generation of the N-bit code values according to the plurality of detected phase differences, and controls the storing of the N-bit code values in an allocated space of the storage by use of a multiplexer configured to provide the plurality of detected phase differences to the N-bit code counter, and a demultiplexer configured to store the N-bit code values in the allocated space of the storage.
摘要翻译：正交相位校正电路包括N比特码计数器，被配置为当执行正交相位校正时根据检测到的相位差产生N比特码值，根据多个检测相位存储N比特码值差异 A控制器共享N位代码计数器，根据多个检测到的相位差控制N位代码值的产生，并且通过使用N位代码值来存储N位代码值到存储器的分配空间中多路复用器，被配置为向N位代码计数器提供多个检测到的相位差，以及解复用器，被配置为将N位代码值存储在存储器的分配空间中。

5. 发明申请

US20090160510A1 BIAS VOLTAGE GENERATION CIRCUIT AND CLOCK SYNCHRONIZING CIRCUIT 有权
标题翻译：偏置电压发生电路和时钟同步电路
公开(公告)号：US20090160510A1
公开(公告)日：2009-06-25
申请号：US12157235
申请日：2008-06-09
申请人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon , Dae-Kun Yoon
发明人： Taek-Sang Song , Kyung-Hoon Kim , Dae-Han Kwon , Dae-Kun Yoon
IPC分类号： H03L7/06 , H03K3/01
CPC分类号： H03L7/0893 , H03L7/099 , H03L7/107 , H03L2207/06
摘要： Bias voltage generator circuit and clock synchronizing circuit includes a bias unit configured to control a current in response to a bandwidth control signal, an amplification unit configured to differentially amplify an input signal in response to the current controlled by the bias unit and an output unit configured to receive an output signal of the amplification unit to output the bias voltage.
摘要翻译：偏置电压发生器电路和时钟同步电路包括被配置为响应于带宽控制信号来控制电流的偏置单元，被配置为响应于由偏置单元控制的电流差异放大输入信号的放大单元和配置的输出单元以接收放大单元的输出信号以输出偏置电压。

6. 发明申请

US20090115467A1 Semiconductor device and operation method thereof 失效
标题翻译：半导体装置及其动作方法
公开(公告)号：US20090115467A1
公开(公告)日：2009-05-07
申请号：US12005515
申请日：2007-12-27
申请人： Dae-Han Kwon , Kyung-Hoon Kim , Dae-Kun Yoon , Taek-Sang Song
发明人： Dae-Han Kwon , Kyung-Hoon Kim , Dae-Kun Yoon , Taek-Sang Song
IPC分类号： H03B19/00 , G06F1/06
CPC分类号： G06F1/06
摘要： A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.
摘要翻译：半导体存储器件可以基于多相时钟信号来优化布局面积和电流消耗，该多相时钟信号是通过使用没有延迟锁定环路和锁相环路的复位信号对源时钟信号进行分频而产生的，以便具有低频和不同的激活时序具有恒定的相位差。

7. 发明申请

US20090115459A1 Semiconductor device and operation method thereof 失效
标题翻译：半导体装置及其动作方法
公开(公告)号：US20090115459A1
公开(公告)日：2009-05-07
申请号：US12005564
申请日：2007-12-27
申请人： Dae-Han Kwon , Kyung-Hoon Kim , Dae-Kun Yoon , Taek-Sang Song
发明人： Dae-Han Kwon , Kyung-Hoon Kim , Dae-Kun Yoon , Taek-Sang Song
IPC分类号： H03K3/017 , H03K5/125
CPC分类号： H03K5/1565
摘要： A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to an operating frequency of the semiconductor device, and a duty ratio detecting unit for detecting a duty ratio of external clock signals in response to the enable signal.
摘要翻译：一种半导体器件，包括：脉冲信号产生单元，用于产生彼此具有不同脉冲宽度的多个脉冲信号;信号复用单元，用于响应于一个或多个脉冲信号输出多个脉冲信号中的一个作为使能信号半导体器件的工作频率以及响应于使能信号检测外部时钟信号的占空比的占空比检测单元。

8. 发明授权

US08283962B2 Semiconductor device and operation method thereof for generating phase clock signals 失效
标题翻译：用于产生相位时钟信号的半导体器件及其操作方法
公开(公告)号：US08283962B2
公开(公告)日：2012-10-09
申请号：US12005515
申请日：2007-12-27
申请人： Dae-Han Kwon , Kyung-Hoon Kim , Dae-Kun Yoon , Taek-Sang Song
发明人： Dae-Han Kwon , Kyung-Hoon Kim , Dae-Kun Yoon , Taek-Sang Song
IPC分类号： H03K3/00
CPC分类号： G06F1/06
摘要： A semiconductor memory device can optimize the layout area and current consumption based on multi-phase clock signals which are generated by dividing a source clock signal using a reset signal without a delay locked loop and a phase locked loop in order to have various phase information of low frequencies and different activation timings with a constant phase difference.
摘要翻译：半导体存储器件可以基于多相时钟信号来优化布局面积和电流消耗，该多相时钟信号是通过使用没有延迟锁定环路和锁相环路的复位信号对源时钟信号进行分频而产生的，以便具有低频和不同的激活时序具有恒定的相位差。

9. 发明授权

US07863955B2 Semiconductor device and operation method thereof 失效
标题翻译：半导体装置及其动作方法
公开(公告)号：US07863955B2
公开(公告)日：2011-01-04
申请号：US12005564
申请日：2007-12-27
申请人： Dae-Han Kwon , Kyung-Hoon Kim , Dae-Kun Yoon , Taek-Sang Song
发明人： Dae-Han Kwon , Kyung-Hoon Kim , Dae-Kun Yoon , Taek-Sang Song
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A semiconductor device includes a pulse signal generating unit for generating a plurality of pulse signals each of which has a different pulse width from each other, a signal multiplexing unit for outputting one of the plurality of the pulse signals as an enable signal in response to frequencies of external clock signals, and a duty ratio detecting unit for detecting a duty ratio of the external clock signals in response to the enable signal.
摘要翻译：一种半导体器件包括：脉冲信号产生单元，用于产生彼此具有不同脉冲宽度的多个脉冲信号;信号复用单元，用于响应于频率输出多个脉冲信号中的一个作为使能信号以及占空比检测单元，用于响应于使能信号检测外部时钟信号的占空比。

10. 发明授权

US07738621B2 Counter with overflow prevention capability 失效
标题翻译：具有防溢出功能的计数器
公开(公告)号：US07738621B2
公开(公告)日：2010-06-15
申请号：US12005933
申请日：2007-12-28
申请人： Dae-Kun Yoon , Kyung-Hoon Kim , Dae-Han Kwon , Taek-Sang Song
发明人： Dae-Kun Yoon , Kyung-Hoon Kim , Dae-Han Kwon , Taek-Sang Song
IPC分类号： G06M3/00 , H03K21/40
CPC分类号： G06M3/12
摘要： A counter with overflow prevention capability includes a counting unit configured to count an output code in response to an input signal and an overflow preventing unit configured to control the counting unit to stop counting the output code when a current value of the output code is a maximum value but a previous value thereof is not the maximum value.
摘要翻译：具有防溢能力的计数器包括：计数单元，被配置为响应于输入信号对输出代码进行计数;以及溢出防止单元，被配置为当输出代码的当前值为最大值时，控制计数单元停止计数输出代码值，但其前一值不是最大值。

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