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1. 发明授权

US07473627B2 Semiconducting device having a structure to improve contact processing margin, and method of fabricating the same 有权
标题翻译：具有改善接触处理余量的结构的半导体器件及其制造方法
公开(公告)号：US07473627B2
公开(公告)日：2009-01-06
申请号：US11502060
申请日：2006-08-09
申请人： Dae Kyeun Kim , Jeong Ho Park
发明人： Dae Kyeun Kim , Jeong Ho Park
IPC分类号： H01L21/3205
CPC分类号： H01L27/11 , H01L21/76897
摘要： A method for fabricating a semiconductor device includes forming a first insulating pattern, a first conductive pattern, and a second conductive pattern on a semiconductor substrate; forming a spacer on sidewalls of the first insulating pattern, the first conductive pattern, and the second conductive pattern; forming a second insulating pattern over the substrate; forming a first salicide on an exposed portion of the substrate and a second salicide on an entire upper surface of the second conductive pattern; depositing a third insulating layer over the substrate, and etching selectively the third insulating layer to forming first and second contact holes exposing the first and second salicides. The method provides processing margin and prevents excessive etching of a conductive layer under the salicide, even if misalignment of an overlying contact hole happens.
摘要翻译：一种制造半导体器件的方法包括在半导体衬底上形成第一绝缘图案，第一导电图案和第二导电图案; 在第一绝缘图案，第一导电图案和第二导电图案的侧壁上形成间隔物; 在所述衬底上形成第二绝缘图案; 在所述基板的暴露部分上形成第一自对准硅化物，在所述第二导电图案的整个上表面上形成第二硅化物; 在衬底上沉积第三绝缘层，并且选择性地蚀刻第三绝缘层以形成暴露第一和第二杀液体的第一和第二接触孔。该方法即使发生上覆接触孔的未对准，也提供了处理余量，并且防止了自对准硅衬底下的导电层的过度蚀刻。

2. 发明授权

US07575989B2 Method of manufacturing a transistor of a semiconductor device 有权
标题翻译：制造半导体器件的晶体管的方法
公开(公告)号：US07575989B2
公开(公告)日：2009-08-18
申请号：US11615780
申请日：2006-12-22
申请人： Jeong Ho Park
发明人： Jeong Ho Park
IPC分类号： H01L21/44
CPC分类号： H01L29/66537 , H01L29/517 , H01L29/518 , H01L29/66621 , H01L29/7834
摘要： A method of manufacturing a transistor in which gate resistance is lowered and short channel effects are controlled by forming a trench-type gate. The threshold voltage can also be more tightly controlled.
摘要翻译：一种制造栅极电阻降低并且通过形成沟槽型栅极控制短沟道效应的晶体管的方法。阈值电压也可以更加严格地控制。

3. 发明授权

US07238573B2 Method for fabricating a trench transistor of semiconductor device 有权
标题翻译：制造半导体器件的沟槽晶体管的方法
公开(公告)号：US07238573B2
公开(公告)日：2007-07-03
申请号：US10748241
申请日：2003-12-31
申请人： Jeong Ho Park
发明人： Jeong Ho Park
IPC分类号： H01L21/336
CPC分类号： H01L29/66621 , H01L29/7834
摘要： A method for fabricating a semiconductor transistor including forming a first insulating layer on a semiconductor substrate; forming an LDD region using ion implantation; patterning the first insulating layer; forming a trench in the substrate; forming a trench gate by depositing and planarizing a second insulating layer and a conductor on the substrate with the trench formed therein; forming a photoresist pattern on the substrate; forming source/drain regions by performing an ion implantation using the photoresist pattern as a mask; and removing the photoresist pattern and the first insulating layer.Thus, a method for fabricating a semiconductor transistor according to the present invention can reduce source/drain resistances and gate resistance by forming a trench type gate and can efficiently control a short channel effect.
摘要翻译：一种制造半导体晶体管的方法，包括在半导体衬底上形成第一绝缘层; 使用离子注入形成LDD区; 图案化第一绝缘层; 在衬底中形成沟槽; 通过在其中形成有沟槽的方式沉积和平坦化衬底上的第二绝缘层和导体来形成沟槽栅; 在所述基板上形成光致抗蚀剂图案; 通过使用光致抗蚀剂图案作为掩模进行离子注入来形成源极/漏极区域; 以及去除光致抗蚀剂图案和第一绝缘层。因此，根据本发明的制造半导体晶体管的方法可以通过形成沟槽型栅极来降低源/漏电阻和栅极电阻，并且可以有效地控制短沟道效应。

4. 发明申请

US20070148883A1 METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE 失效
标题翻译：制造半导体器件的方法
公开(公告)号：US20070148883A1
公开(公告)日：2007-06-28
申请号：US11615652
申请日：2006-12-22
申请人： Jeong Ho Park
发明人： Jeong Ho Park
IPC分类号： H01L21/336
CPC分类号： H01L21/76224 , H01L29/66795 , H01L29/785
摘要： Embodiments relate to a method of manufacturing a semiconductor device. According to embodiments, the method may include forming a first and a second insulating layer on a semiconductor substrate of which an active area and an isolation region are defined, forming a first and a second insulating layer pattern by selectively removing the first and the second insulating layer to expose the isolation region of the semiconductor substrate, forming a trench having a prescribed depth by selectively removing the semiconductor substrate by using the first and the second insulating layer pattern as a mask, forming an isolation layer as a third insulating layer in the trench, removing a prescribed thickness of the isolation layer from the surface portion through etching the whole semiconductor substrate while remaining at the side portions of the first and second insulating layer pattern and the active area as a side wall shape, removing the first and the second insulating layer pattern, and removing a prescribed thickness of the isolation layer from the surface portion to protrude the active area of the semiconductor substrate.
摘要翻译：实施例涉及制造半导体器件的方法。根据实施例，该方法可以包括在其上限定有源区和隔离区的半导体衬底上形成第一绝缘层和第二绝缘层，通过选择性地去除第一和第二绝缘层形成第一和第二绝缘层图案以暴露半导体衬底的隔离区域，通过使用第一和第二绝缘层图案作为掩模选择性地去除半导体衬底，形成具有规定深度的沟槽，在沟槽中形成隔离层作为第三绝缘层通过蚀刻整个半导体衬底同时保留在第一和第二绝缘层图案和有源区域的侧部作为侧壁形状，从表面部分去除规定厚度的隔离层，去除第一和第二绝缘体并且从表面孔去除隔离层的规定厚度突出半导体衬底的有源区。

5. 发明授权

US07071057B2 Methods of fabricating MIM capacitors of semiconductor devices 有权
标题翻译：制造半导体器件的MIM电容器的方法
公开(公告)号：US07071057B2
公开(公告)日：2006-07-04
申请号：US11027312
申请日：2004-12-30
申请人： Jeong Ho Park
发明人： Jeong Ho Park
IPC分类号： H01L21/8242
CPC分类号： H01L21/76808 , H01L21/76802 , H01L23/5223 , H01L27/1085 , H01L27/10897 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating a MIM capacitor and a dual damascene structure of a semiconductor device are disclosed. A disclosed method comprises forming a first conducting material as a lower interconnect on a semiconductor substrate; sequentially depositing second and third insulating layers over the first conducting layer; performing a first damascene process to form via holes and a trench within the second and the third insulating layers; filling the via holes and the trench to form a first contact plug connected to a lower interconnect and a second contact plug to contact the lower electrode of a MIM capacitor; forming the MIM capacitor over the second contact plug; sequentially depositing fourth and fifth insulating layers over the entire surface of the resulting structure; performing a second damascene process to form a via hole and a trench within the fourth and the fifth insulating layers; and filling the via hole and the trench to form a contact plug in contact with the upper electrode of the capacitor and another contact plug connected to the lower metal interconnect.
摘要翻译：公开了制造半导体器件的MIM电容器和双镶嵌结构的方法。所公开的方法包括在半导体衬底上形成作为下互连的第一导电材料; 在第一导电层上依次沉积第二和第三绝缘层; 执行第一镶嵌工艺以在第二和第三绝缘层内形成通孔和沟槽; 填充通孔和沟槽以形成连接到下互连的第一接触插塞和与MIM电容器的下电极接触的第二接触插塞; 在所述第二接触插塞上形成所述MIM电容器; 在所得结构的整个表面上依次沉积第四和第五绝缘层; 执行第二镶嵌工艺以在第四绝缘层和第五绝缘层内形成通孔和沟槽; 并且填充通孔和沟槽以形成与电容器的上电极接触的接触插塞和连接到下金属互连的另一接触插塞。

6. 发明授权

US07071054B2 Methods of fabricating MIM capacitors in semiconductor devices 有权
标题翻译：在半导体器件中制造MIM电容器的方法
公开(公告)号：US07071054B2
公开(公告)日：2006-07-04
申请号：US11027524
申请日：2004-12-30
申请人： Jeong Ho Park
发明人： Jeong Ho Park
IPC分类号： H01L21/8242
CPC分类号： H01L21/7681 , H01L23/5223 , H01L27/1085 , H01L27/10897 , H01L28/91 , H01L2924/0002 , H01L2924/00
摘要： Methods of fabricating an MIM capacitor and a dual damascene structure of a semiconductor device are disclosed. According to one example, a method includes depositing a first insulating layer on a semiconductor substrate; forming a lower interconnect through the first insulating layer; sequentially depositing a second insulating layer, a third insulating layer, and a fourth insulating layer; forming a first mask pattern over the fourth insulating layer; forming a first dual damascene pattern by etching the fourth insulating layer; depositing a fifth insulating layer; forming a second mask pattern over the fifth insulating layer; forming dual damascene structure by performing an etching process; sequentially depositing a second conducting layer and a dielectric layer on the dual damascene structure; selectively removing some portion of the dielectric layer; depositing a third conducting layer over the dielectric layer; and planarizaing the top surface of the third conducting layer, the dielectric layer, and the second conducting layer by performing a CMP process.
摘要翻译：公开了制造半导体器件的MIM电容器和双镶嵌结构的方法。根据一个示例，一种方法包括在半导体衬底上沉积第一绝缘层; 通过所述第一绝缘层形成下互连; 依次沉积第二绝缘层，第三绝缘层和第四绝缘层; 在所述第四绝缘层上形成第一掩模图案; 通过蚀刻第四绝缘层形成第一双镶嵌图案; 沉积第五绝缘层; 在所述第五绝缘层上形成第二掩模图案; 通过进行蚀刻工艺形成双镶嵌结构; 在双镶嵌结构上依次沉积第二导电层和介电层; 选择性地去除介电层的一部分; 在所述电介质层上沉积第三导电层; 并且通过执行CMP处理来平坦化第三导电层，电介质层和第二导电层的顶表面。

7. 发明授权

US07880233B2 Transistor with raised source and drain formed on SOI substrate 有权
标题翻译：在SOI衬底上形成具有升高的源极和漏极的晶体管
公开(公告)号：US07880233B2
公开(公告)日：2011-02-01
申请号：US12579444
申请日：2009-10-15
申请人： Jeong Ho Park
发明人： Jeong Ho Park
IPC分类号： H01L29/786
CPC分类号： H01L29/458 , H01L29/66772
摘要： Embodiments relate to a method for fabricating a transistor by using a SOI wafer. A gate insulation layer and a first gate conductive layer on a silicon-on-insulator substrate of a substrate to form a first gate conductive pattern, a gate insulation layer pattern, and a silicon layer pattern. A device isolation insulation layer exposing the top surface of the first gate conductive layer pattern may be formed. A second gate conductive layer may be formed. A mask pattern may be formed. Then, a gate may be formed by etching. After forming a source and drain conductive layer on the silicon layer pattern, the mask pattern may be removed. A salicide layer may be selectively contacting the gate and the source and drain conductive layer may be formed.
摘要翻译：实施例涉及通过使用SOI晶片制造晶体管的方法。栅极绝缘层和位于衬底上的硅绝缘体衬底上的第一栅极导电层，以形成第一栅极导电图案，栅极绝缘层图案和硅层图案。可以形成暴露第一栅极导电层图案的顶表面的器件隔离绝缘层。可以形成第二栅极导电层。可以形成掩模图案。然后，可以通过蚀刻形成栅极。在硅层图案上形成源极和漏极导电层之后，可以去除掩模图案。自对准硅层可以选择性地接触栅极，并且可以形成源极和漏极导电层。

8. 发明授权

US07393750B2 Method for manufacturing a semiconductor device 失效
标题翻译：半导体器件的制造方法
公开(公告)号：US07393750B2
公开(公告)日：2008-07-01
申请号：US11615652
申请日：2006-12-22
申请人： Jeong Ho Park
发明人： Jeong Ho Park
IPC分类号： H01L21/8242 , H01L21/336
CPC分类号： H01L21/76224 , H01L29/66795 , H01L29/785
摘要： Embodiments relate to a method of manufacturing a semiconductor device. According to embodiments, the method may include forming a first and a second insulating layer on a semiconductor substrate of which an active area and an isolation region are defined, forming a first and a second insulating layer pattern by selectively removing the first and the second insulating layer to expose the isolation region of the semiconductor substrate, forming a trench having a prescribed depth by selectively removing the semiconductor substrate by using the first and the second insulating layer pattern as a mask, forming an isolation layer as a third insulating layer in the trench, removing a prescribed thickness of the isolation layer from the surface portion through etching the whole semiconductor substrate while remaining at the side portions of the first and second insulating layer pattern and the active area as a side wall shape, removing the first and the second insulating layer pattern, and removing a prescribed thickness of the isolation layer from the surface portion to protrude the active area of the semiconductor substrate.
摘要翻译：实施例涉及制造半导体器件的方法。根据实施例，该方法可以包括在其上限定有源区和隔离区的半导体衬底上形成第一绝缘层和第二绝缘层，通过选择性地去除第一和第二绝缘层形成第一和第二绝缘层图案以暴露半导体衬底的隔离区域，通过使用第一和第二绝缘层图案作为掩模选择性地去除半导体衬底，形成具有规定深度的沟槽，在沟槽中形成隔离层作为第三绝缘层通过蚀刻整个半导体衬底同时保留在第一和第二绝缘层图案和有源区域的侧部作为侧壁形状，从表面部分去除规定厚度的隔离层，去除第一和第二绝缘体并且从表面孔去除隔离层的规定厚度突出半导体衬底的有源区。

9. 发明授权

US07348254B2 Method of fabricating fin field-effect transistors 有权
标题翻译：散射场效应晶体管的制造方法
公开(公告)号：US07348254B2
公开(公告)日：2008-03-25
申请号：US11319261
申请日：2005-12-29
申请人： Jeong Ho Park
发明人： Jeong Ho Park
IPC分类号： H01L21/76
CPC分类号： H01L29/7851 , H01L29/665 , H01L29/66795
摘要： A method of fabricating a fin field-effect transistor that may enable a reduction in the number of process steps, by forming the fin structure by etching away a predetermined thickness of an element isolation layer. The method includes steps of sequentially forming a first insulating layer and a second insulating layer on a region of a substrate excluding an inactive region thereof; forming a trench of the inactive region of the substrate by using the first and second insulating layers as a mask; forming an element isolation layer in the trench; and removing the first insulating layer and the second insulating layer and, at the same time, removing a predetermined thickness of the element isolation layer.
摘要翻译：一种制造鳍状场效应晶体管的方法，其可以通过蚀刻除去元件隔离层的预定厚度来形成鳍结构，从而可以减少工艺步骤的数量。该方法包括以下步骤：在除了其非活性区域之外的衬底的区域上顺序地形成第一绝缘层和第二绝缘层; 通过使用第一绝缘层和第二绝缘层作为掩模，形成衬底的非活性区域的沟槽; 在沟槽中形成元件隔离层; 以及去除所述第一绝缘层和所述第二绝缘层，并且同时去除所述元件隔离层的预定厚度。

10. 发明授权

US07211495B2 Semiconductor devices having a capacitor and methods of manufacturing the same 有权
标题翻译：具有电容器的半导体器件及其制造方法
公开(公告)号：US07211495B2
公开(公告)日：2007-05-01
申请号：US10960216
申请日：2004-10-06
申请人： Jeong Ho Park
发明人： Jeong Ho Park
IPC分类号： H01L21/027 , H01L21/71
CPC分类号： H01L23/53295 , H01L21/76846 , H01L23/5223 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices having a capacitor and methods of manufacturing the same are disclosed. A disclosed semiconductor device includes a semiconductor substrate; a lower interconnection line on the substrate; an upper interconnection line electrically connected to a first portion of the lower interconnection line; a first metal layer electrically connected to a second portion of the lower interconnection line; a capacitor insulating layer on the first metal layer; and a second metal layer on the capacitor insulating layer, wherein the first metal layer, the capacitor insulating layer and the second metal layer form a capacitor
摘要翻译：公开了具有电容器的半导体器件及其制造方法。所公开的半导体器件包括半导体衬底; 衬底上的下互连线; 电连接到下互连线的第一部分的上互连线; 电连接到下互连线的第二部分的第一金属层; 第一金属层上的电容器绝缘层; 以及所述电容器绝缘层上的第二金属层，其中所述第一金属层，所述电容器绝缘层和所述第二金属层形成电容器

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