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    • 2. 发明申请
    • METHOD AND VIDEO SYSTEM FOR FREEZE-FRAME DETECTION
    • 用于冻结框架检测的方法和视频系统
    • US20160037186A1
    • 2016-02-04
    • US14445718
    • 2014-07-29
    • DIRK WENDELJOACHIM FADERSTEPHAN HERRMANNWILHARD CHRISTOPHORUS VON WENDORFF
    • DIRK WENDELJOACHIM FADERSTEPHAN HERRMANNWILHARD CHRISTOPHORUS VON WENDORFF
    • H04N19/89H04N19/66H04N19/46
    • H04N19/89
    • A method for detecting a freeze-frame condition comprises receiving a sequence of images from at least one digital device; selectively encoding a first subset of the sequence of images using a first coding scheme that causes an adjustment to an image characteristic of the selected images being encoded; selectively encoding a second subset of the sequence of images using a second coding scheme; storing the first encoded subset and second encoded subset; retrieving the stored first encoded subset and second encoded subset; selectively decoding the first subset of the selected images using the first coding scheme and selectively decoding the second subset of the selected images using the second coding scheme to re-create the sequence of images. A freeze-frame condition in the re-created sequence of images is identifiable based on a plurality of decoded images being different with respect to the image characteristic across multiple decoded image frames.
    • 一种用于检测冻结帧状况的方法包括从至少一个数字设备接收一系列图像; 使用导致对被编码的所选择的图像的图像特征进行调整的第一编码方案来选择性地编码图像序列的第一子集; 使用第二编码方案选择性地编码图像序列的第二子集; 存储第一编码子集和第二编码子集; 检索所存储的第一编码子集和第二编码子集; 使用第一编码方案选择性地解码所选图像的第一子集,并且使用第二编码方案选择性地解码所选图像的第二子集以重新创建图像序列。 基于多个解码图像相对于跨多个解码图像帧的图像特征而不同的图像重新创建序列中的冻结帧条件是可识别的。
    • 3. 发明申请
    • OSCILLATOR CIRCUIT AND METHOD OF GENERATING A CLOCK SIGNAL
    • 振荡器电路和产生时钟信号的方法
    • US20160132070A1
    • 2016-05-12
    • US14899170
    • 2013-07-04
    • Hubert BODEDirk WENDEL
    • HUBERT BODEDIRK WENDEL
    • G06F1/08H03K3/023
    • G06F1/08H03K3/023H03K3/0231
    • An oscillator circuit of the type comprising a flip-flop for generating a clock signal and two comparators for comparing a reference voltage with the voltage across a first capacitor which is charged during a first cycle of the clock signal and the voltage across a second capacitor which is charged during a second cycle of a clock signal provides a means for removing the effects of any offset in either comparator. This is achieved by reversing the inputs of the comparators for each cycle of the output frequency. Thus an offset in a comparator which would increase the clock period on one cycle will reduce the period of the next cycle by the same amount. As a net result, the period of time over two clock periods will stay constant regardless of any offset drift in a comparator.
    • 一种振荡器电路,包括用于产生时钟信号的触发器和用于将参考电压与在第一电容器的第一周期期间充电的第一电容器两端的电压进行比较的两个比较器,以及跨越第二电容器的电压 在时钟信号的第二周期期间被充电提供了用于消除任一比较器中任何偏移的影响的装置。 这是通过在输出频率的每个周期反转比较器的输入来实现的。 因此,将在一个周期上增加时钟周期的比较器中的偏移将使下一个周期的周期减少相同的量。 作为最终结果,无论比较器中有任何偏移漂移,两个时钟周期的时间段将保持不变。
    • 4. 发明申请
    • INTEGRATED CIRCUIT AND METHOD OF DETECTING A DATA INTEGRITY ERROR
    • 集成电路和检测数据完整性错误的方法
    • US20160077904A1
    • 2016-03-17
    • US14483262
    • 2014-09-11
    • DIRK WENDELMICHAEL ROHLEDERROLF SCHLAGENHAFT
    • DIRK WENDELMICHAEL ROHLEDERROLF SCHLAGENHAFT
    • G06F11/07
    • G06F11/079G06F11/0736G06F11/0751G06F11/0772
    • An integrated circuit comprises a write bus coupled to a register for storing control data. A storage unit is arranged to store reference signature data encoding a reference collective state of the register. First logic circuitry generates actual signature data encoding the actual collective state of the register. Second logic circuitry is coupled to the storage unit, receives the actual signature data and compares the actual signature data with the reference signature data. The second logic circuitry comprises an alert output to provide an alert signal in response to the comparison identifying a difference between the actual signature data and the reference signature data, thereby ensuring detection of a data integrity error in respect of the register. An alert inhibitor comprises a control input and is responsive to the control input and arranged to inhibit selectively onward propagation of the alert signal from the alert output.
    • 集成电路包括耦合到用于存储控制数据的寄存器的写总线。 存储单元被布置为存储编码寄存器的参考集合状态的参考签名数据。 第一逻辑电路生成编码寄存器的实际集体状态的实际签名数据。 第二逻辑电路耦合到存储单元,接收实际签名数据并将实际签名数据与参考签名数据进行比较。 第二逻辑电路包括警报输出,以响应于比较来识别实际签名数据和参考签名数据之间的差异来提供警报信号,从而确保检测关于该寄存器的数据完整性错误。 警报抑制器包括控制输入并且响应于控制输入并被布置成禁止警报信号从警报输出中选择性地向前传播。