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1. 发明申请

US20150220410A1 MECHANISM FOR ACHIEVING HIGH MEMORY RELIABLITY, AVAILABILITY AND SERVICEABILITY 审中-公开
标题翻译：实现高记忆可靠性，可用性和可维护性的机制
公开(公告)号：US20150220410A1
公开(公告)日：2015-08-06
申请号：US14563761
申请日：2014-12-08
申请人： DABLEENA DAS , Kai Cheng , Jonathan C. Jasper
发明人： DABLEENA DAS , Kai Cheng , Jonathan C. Jasper
IPC分类号： G06F11/20 , G06F11/10
CPC分类号： G06F11/2094 , G06F11/1044 , G06F11/1076 , H03M13/05
摘要： A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.
摘要翻译：描述了根据本发明的一个实施例的用于实现高存储器可靠性，可用性和可服务性（RAS）的机制。本发明的实施例的方法包括：检测在计算系统处的存储器系统的第一通道的多个存储器件的第一存储器件的永久故障，并通过合并第一纠错码来消除第一故障（ ECC）具有第二信道的第二ECC定位器装置的第一信道的定位装置，其中在第二信道执行合并。

2. 发明授权

US08914704B2 Mechanism for achieving high memory reliablity, availability and serviceability 有权
标题翻译：实现高内存可靠性，可用性和可维护性的机制
公开(公告)号：US08914704B2
公开(公告)日：2014-12-16
申请号：US13538922
申请日：2012-06-29
申请人： Debaleena Das , Kai Cheng , Jonathan C. Jasper
发明人： Debaleena Das , Kai Cheng , Jonathan C. Jasper
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/2094 , G06F11/1044 , G06F11/1076 , H03M13/05
摘要： A mechanism is described for achieving high memory reliability, availability, and serviceability (RAS) according to one embodiment of the invention. A method of embodiments of the invention includes detecting a permanent failure of a first memory device of a plurality of memory devices of a first channel of a memory system at a computing system, and eliminating the first failure by merging a first error-correction code (ECC) locator device of the first channel with a second ECC locator device of a second channel, wherein merging is performed at the second channel.
摘要翻译：描述了根据本发明的一个实施例的用于实现高存储器可靠性，可用性和可服务性（RAS）的机制。本发明的实施例的方法包括：检测在计算系统处的存储器系统的第一通道的多个存储器件的第一存储器件的永久故障，并通过合并第一纠错码来消除第一故障（ ECC）具有第二信道的第二ECC定位器装置的第一信道的定位装置，其中在第二信道执行合并。

3. 发明授权

US6109929A High speed stackable memory system and device 失效
标题翻译：高速可堆叠内存系统和设备
公开(公告)号：US6109929A
公开(公告)日：2000-08-29
申请号：US124424
申请日：1998-07-29
申请人： Jonathan C. Jasper
发明人： Jonathan C. Jasper
IPC分类号： G06F1/18 , G11C5/00 , H05K1/14 , H05K7/02 , H01R12/00 , H05K1/00
CPC分类号： G06F1/185 , G06F1/184 , G06F1/186 , H05K1/144 , H05K7/023 , H01R12/7011 , H01R12/716
摘要： A stackable memory system for minimizing the stub lengths of the memory data bus and data skew. The invention provides a memory controller, a memory connector, a data bus, a first stackable memory module and a terminator plate. The data bus electrically connects the controller to the memory connector. The first stackable memory module is mechanically and electrically connected to the memory connector. The terminator plate is adapted to substantially reduce reflections to the data bus and is electrically connected to the data bus through the first stackable memory module. Additional, the memory system may be expanded by adding stackable memory modules substantially similar to the first stackable memory module to the stackable memory system between the first memory module and the terminator plate. Each stackable memory module may include memory chips each of which has trace lines connecting the memory chip to a module connector. Each of the trace lines is substantially equal in length and connects to a single side of the memory chip.
摘要翻译：用于最小化存储器数据总线的短截线长度和数据偏移的可堆叠存储器系统。本发明提供一种存储器控制器，存储器连接器，数据总线，第一可堆叠存储器模块和终端板。数据总线将控制器电连接到存储器连接器。第一可堆叠存储器模块机械地和电连接到存储器连接器。终端板适于基本上减少对数据总线的反射，并且通过第一可堆叠存储器模块电连接到数据总线。此外，可以通过将基本上类似于第一可堆叠存储器模块的可堆叠存储器模块添加到第一存储器模块和终端板之间的可堆叠存储器系统来扩展存储器系统。每个可堆叠存储器模块可以包括存储器芯片，每个存储器芯片具有将存储器芯片连接到模块连接器的迹线。每条迹线的长度基本相等，并连接到存储芯片的单侧。

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