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1. 发明授权

US07028150B2 Arrangement of data within cache lines so that tags are first data received 有权
公开(公告)号：US07028150B2
公开(公告)日：2006-04-11
申请号：US10226418
申请日：2002-08-23
申请人： Curtis R. McAllister , Robert C. Douglas , Henry Yu
发明人： Curtis R. McAllister , Robert C. Douglas , Henry Yu
IPC分类号： G06F11/00
CPC分类号： G06F12/0831 , G06F12/0822
摘要： A memory system and method for processing a data structure comprising a plurality of data bits representing a line of memory, wherein the data bits are divided into a plurality of data chunks, each of the data chunks including at least an error correction code portion and a data portion; and a first chunk of said plurality of data chunks having a tag portion, wherein said tag portion includes tag information for the entire line of memory, and wherein subsequent ones of said data chunks do not include tag information.

2. 发明授权

US06463506B1 Arrangement of data within cache lines so that tags are first data received 有权
标题翻译：高速缓存行内数据的排列，使标签首先接收到数据
公开(公告)号：US06463506B1
公开(公告)日：2002-10-08
申请号：US09562592
申请日：2000-04-29
申请人： Curtis R. McAllister , Robert C. Douglas , Henry Yu
发明人： Curtis R. McAllister , Robert C. Douglas , Henry Yu
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0822
摘要： A memory system includes a main memory controller supplying data in response to transactions received by the main memory controller. A plurality of modules each include a cache memory for storing data supplied by the main memory controller. The modules request data from the main memory controller by sending module generated transactions to the main memory controller. A cache tag array includes a cache tag corresponding to each data line stored in memory, there being a one-to-one correspondence between the cache tags and the data lines. The data lines together with their associated cache tags are combined and arranged in a plurality of sequential data chunks, the cache tags included in an initial portion of the data chunks (i.e, a first sequence of bits) followed by inclusion of the data lines in a subsequent portion of the data chunks (i.e., the usable bit positions following inclusion of all of the cache tag bits.) Each of the chunks may further include appropriate ECC bits. By this arrangement, all of the cache tags are transferred between the main memory controller and the plurality of modules prior to transfer of the bits constituting the data lines so that any coherency operations may be initiated without waiting to receive the remaining data of the data line.
摘要翻译：存储器系统包括主存储器控制器，其响应于由主存储器控制器接收的事务提供数据。多个模块各自包括用于存储由主存储器控制器提供的数据的高速缓冲存储器。模块通过将模块生成的事务发送到主存储器控制器来请求来自主存储器控制器的数据。高速缓存标签阵列包括对应于存储在存储器中的每条数据线的高速缓存标签，高速缓存标签与数据线之间存在一对一的对应关系。数据线及其相关联的高速缓存标签被组合并排列在多个顺序数据块中，高速缓存标签包括在数据块的初始部分中（即，第一比特序列），随后将数据线包括在数据块的后续部分（即，包括所有高速缓存标签位之后的可用位位置）。每个块可以进一步包括适当的ECC位。通过这种安排，在传输构成数据线的位之前，所有高速缓存标签在主存储器控制器和多个模块之间传送，使得可以发起任何一致性操作而不等待接收数据线的剩余数据。

3. 发明授权

US06928520B2 Memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent 有权
标题翻译：通过使用至少一个内存控制器代理提供内存线缓存和内存事务一致性的内存控制器
公开(公告)号：US06928520B2
公开(公告)日：2005-08-09
申请号：US10437677
申请日：2003-05-14
申请人： Curtis R. McAllister , Robert C. Douglas
发明人： Curtis R. McAllister , Robert C. Douglas
IPC分类号： G06F12/08
CPC分类号： G06F12/0828 , G06F12/084
摘要： Embodiments of the present invention include a memory controller that provides memory line caching and memory transaction coherency by using at least one memory controller agent. The memory controller includes at least one memory-controller agent, an incoming memory-transaction dispatch unit, and an outgoing memory-transaction completion unit. Each memory-controller agent has a memory-line memory controller and a memory-line coherency controller, along with a cache memory capable of caching the contents of a memory line along with coherency information for the memory line. Memory transactions are received from cacheable entities of a computer system at the incoming memory-transaction dispatch unit, and are then presented to one or more agents. If multiple memory-read transactions are received for a single memory line, the agents will configure themselves into a linked list to queue up the requests.
摘要翻译：本发明的实施例包括通过使用至少一个存储器控制器代理来提供存储器线缓存和存储器事务一致性的存储器控制器。存储器控制器包括至少一个存储器控制器代理，进入存储器事务分派单元和输出存储器交易完成单元。每个存储器控制器代理具有存储器行存储器控制器和存储器线路一致性控制器，以及能够缓存存储器线的内容以及存储器线的一致性信息的高速缓存存储器。从存储器 - 事务处理单元处的计算机系统的可缓存实体接收内存事务，然后将其呈现给一个或多个代理。如果为单个内存线接收到多个内存读取事务，代理将自己配置为链接列表以排队请求。

4. 发明授权

US06611906B1 Self-organizing hardware processing entities that cooperate to execute requests 失效
标题翻译：合作执行请求的自组织硬件处理实体
公开(公告)号：US06611906B1
公开(公告)日：2003-08-26
申请号：US09560928
申请日：2000-04-30
申请人： Curtis R. McAllister , Robert C. Douglas
发明人： Curtis R. McAllister , Robert C. Douglas
IPC分类号： G06F1208
CPC分类号： G06F13/1673
摘要： A hardware-based linked list queues memory transactions in a memory controller. The memory controller includes a plurality of memory controller agents. Each agent has a head flag, a tail flag, and a next agent field, thereby allowing the agents to be arranged into linked lists. Memory transactions are received from cacheable entities of a computer system at an incoming memory transaction dispatch unit via an interconnection fabric. The incoming transactions are then presented to the plurality of agents. For each incoming read transaction, one of the agents will accept the transaction. If there are pending memory read transactions for the memory line, then the accepting agent joins a linked list of agents that are queued up to access that memory line. The accepting agent drives its index out onto a bus that connects all agents. One agent in the linked list will have its tail flag set, and that agent will clear its tail flag and latch into its next agent field the index provided by the accepting agent. Also, the accepting agent will set its tail flag to indicate that it is now at the end of the linked list. When the head agent finishes a transaction, the head agent advances the list by notifying the next agent that it is now the new head agent. The old head agent then clears a valid flag, indicating that it can now accept a new transaction, and the new head agent sets its head flag.
摘要翻译：基于硬件的链表列出了内存控制器中的内存事务。存储器控制器包括多个存储器控制器代理。每个代理具有头标志，尾标和下一代理字段，从而允许代理被布置成链表。通过互连结构，在进入的存储器事务处理单元从计算机系统的可缓存实体接收内存事务。然后将传入的事务呈现给多个代理。对于每个传入的读取事务，其中一个代理将接受事务。如果内存行有待处理的内存读取事务，则接受代理程序加入排队等待访问该内存行的代理的链接列表。接受代理将其索引驱动到连接所有代理的总线上。链接列表中的一个代理将设置其尾标志，并且该代理将清除其尾标并将其锁定到其接下来的代理字段中，该代理字段由接受代理提供。此外，接受代理将设置其尾标记以指示它现在在链表的末尾。当总代理完成交易时，头号代理人通过通知下一代理人来预先列表它现在是新的代理。然后，旧的头代理清除一个有效的标志，表示它现在可以接受一个新的事务，并且新的头代理设置其头标志。

5. 发明授权

US06598140B1 Memory controller having separate agents that process memory transactions in parallel 失效
标题翻译：内存控制器具有并行处理内存事务的独立代理
公开(公告)号：US06598140B1
公开(公告)日：2003-07-22
申请号：US09560927
申请日：2000-04-30
申请人： Curtis R. McAllister , Robert C. Douglas
发明人： Curtis R. McAllister , Robert C. Douglas
IPC分类号： G06F1208
CPC分类号： G06F13/1631 , G06F12/0828 , G06F12/084
摘要： A memory controller has separate memory controller agents that process memory transactions in parallel. A memory controller in accordance with the present invention includes a plurality of memory controller agents, which are coupled to each other via a series of busses, an incoming memory transaction dispatch unit, and an outgoing memory dispatch unit. Memory transactions are received from cacheable entities of a computer system at the incoming memory transaction dispatch unit, and are then presented to the plurality of agents. For each incoming transaction, one of the agents will accept the transaction. Each agent is responsible for ensuring coherency and fulfilling memory transactions for a single memory line. If multiple memory read transactions are received for a single memory line, the agents will configure themselves into a linked list to queue up the requests. The coherency information and memory line data associated with each memory line may be cached by each agent, thereby allowing repeated requests to the same memory line to be serviced more quickly. When two or more agents are queued up to fulfill multiple memory read transactions to the same memory line, the agents cooperate by transferring the coherency information and memory line data associated with each memory line from agent to agent, thereby minimizing the need to access main memory. The agents complete memory transactions back to the cacheable entities via the outgoing memory dispatch unit.
摘要翻译：内存控制器具有独立的内存控制器代理，可以并行处理内存事务。根据本发明的存储器控制器包括多个存储器控制器代理，其经由一系列总线相互耦合，输入存储器事务调度单元和输出存储器调度单元。从存储器事务处理单元处的计算机系统的可缓存实体接收存储器事务，然后将其呈现给多个代理。对于每个传入的事务，其中一个代理将接受事务。每个代理负责确保单个内存线的一致性和完成内存事务。如果为单个内存线接收到多个内存读取事务，代理将自己配置为链接列表以排队请求。与每个存储器线相关联的一致性信息和存储器线数据可以由每个代理缓存，从而允许对同一存储器线的重复请求更快地被服务。当两个或多个代理队列排队等待到同一存储器线路的多个存储器读取事务时，代理通过将与每个存储器线相关联的一致性信息和存储器线路数据从代理转移到代理进行协作，从而最小化访问主存储器的需要。代理通过输出内存分派单元完成内存事务回到可缓存实体。

6. 发明授权

US06480943B1 Memory address interleaving and offset bits for cell interleaving of memory 失效
标题翻译：存储器地址交织和用于存储器的单元交织的偏移位
公开(公告)号：US06480943B1
公开(公告)日：2002-11-12
申请号：US09563018
申请日：2000-04-29
申请人： Robert C. Douglas , Kent A. Dickey
发明人： Robert C. Douglas , Kent A. Dickey
IPC分类号： G06F1200
CPC分类号： G06F12/0607
摘要： A method provides for interleaved access of a contiguous logical address space formed by a plurality of memories having respective overlapping address spaces. The memories are organized into memory segments, memory segments of equal size from different memories arranged or organized into interleave groups. An initial largest interleave group is selected and a corresponding first interleave entry is generated in a table. The interleave entry maps a corresponding initial logical address space into each of the memory segments corresponding to the first interleave group. A total memory size included thus far in the table is calculated and successive next larger groups that are integer divisors of the total memory, i.e., the partial sums formed by groups selected thus far. These steps are repeated until all of the contiguous logical address space has been mapped onto the memories. A mask may be used to extract portions from a logical address to index into a table mapping the logical address space onto the memories. Another portion of the logical address includes a memory offset.
摘要翻译：一种方法提供由具有相应重叠地址空间的多个存储器形成的连续逻辑地址空间的交织访问。存储器被组织成存储器段，从布置或组织成交织组的不同存储器的相同尺寸的存储器段。选择初始最大交织组，并在表中生成对应的第一交织条目。交织条目将对应的初始逻辑地址空间映射到与第一交织组对应的每个存储器段中。计算出到目前为止在表中包括的总存储器大小，以及作为总存储器的整数除数的连续的下一较大组，即由迄今为止选择的组形成的部分和。重复这些步骤，直到所有连续的逻辑地址空间已经映射到存储器上。可以使用掩码将逻辑地址中的部分提取到索引到将逻辑地址空间映射到存储器的表中。逻辑地址的另一部分包括存储器偏移。

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