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1. 发明授权

US06708286B2 Standby SBC backplane 失效
标题翻译：待机SBC背板
公开(公告)号：US06708286B2
公开(公告)日：2004-03-16
申请号：US10235513
申请日：2002-09-04
申请人： Curtis R. Alexander , Alonso Perez , Thang Doan
发明人： Curtis R. Alexander , Alonso Perez , Thang Doan
IPC分类号： G06F1100
CPC分类号： G06F11/2033 , G06F11/2025
摘要： A computer system comprising a first computer coupled to a primary PCI bus via a first PCI bus switch and a second computer coupled to the primary PCI bus via a second PCI bus switch. A monitor system is coupled to both the first and second computers as well as the first and second PCI bus switches. In the event of a malfunction in the first computer, the monitor system decouples the first computer from the primary PCI bus, by opening the first PCI bus switch and coupling the second computer to the primary PCI bus by closing the second PCI bus switch.
摘要翻译：一种计算机系统，包括经由第一PCI总线开关耦合到主PCI总线的第一计算机和经由第二PCI总线交换机耦合到主PCI总线的第二计算机。监视器系统耦合到第一和第二计算机以及第一和第二PCI总线开关。在第一台计算机发生故障的情况下，监控系统通过打开第一个PCI总线开关将第一台计算机与主PCI总线分离，并通过关闭第二个PCI总线开关将第二台计算机连接到主PCI总线。

2. 发明授权

US06510529B1 Standby SBC backplate 失效
标题翻译：待机SBC背板
公开(公告)号：US06510529B1
公开(公告)日：2003-01-21
申请号：US09397844
申请日：1999-09-15
申请人： Curtis R. Alexander , Alonso Perez , Thang Doan
发明人： Curtis R. Alexander , Alonso Perez , Thang Doan
IPC分类号： H02H305
CPC分类号： G06F11/2033 , G06F11/2025
摘要： A computer system employs a first computer; a first bus switch coupled to the first computer; a data bus coupled to the first computer via the first bus switch; a second computer; a second bus switch coupled to the second computer, the data bus being coupled to the second computer through the second bus switch; and a monitor system coupled to the first computer, to the first bus switch, and to the second bus switch. The monitor system employs a watchdog timer coupled to a switch over circuit, wherein a watchdog timeout period exceeds a period between executions of a reset code, the reset code being included in software executing on the first computer, wherein a reset signal is generated in response to execution of the reset code, thereby resetting the watchdog timer prior to the watchdog timeout period, and wherein upon a failure in the first computer the reset code is not executed, and therefore the reset signal is not generated, thereby not resetting the watchdog timer prior to the watchdog timeout period, wherein the watchdog timer generates a switch over signal in the event the watchdog timeout period is reached before the watchdog timer is reset, wherein the switch over circuit opens the first data bus switch and closes the second data bus switch in response to the switch over signal.
摘要翻译：计算机系统采用第一计算机; 耦合到第一计算机的第一总线开关; 数据总线，经由第一总线开关耦合到第一计算机; 第二台电脑耦合到所述第二计算机的第二总线开关，所述数据总线通过所述第二总线开关耦合到所述第二计算机; 以及耦合到第一计算机，第一总线开关和第二总线开关的监视器系统。监视器系统采用耦合到切换电路的看门狗定时器，其中看门狗超时周期超过复位代码执行之间的周期，复位代码被包括在第一计算机上执行的软件中，其中响应中产生复位信号执行复位代码，从而在看门狗超时周期之前复位看门狗定时器，并且其中当第一计算机中的故障不执行复位代码时，因此不产生复位信号，从而不复位看门狗定时器在看门狗超时周期之前，其中看门狗定时器在看门狗定时器复位之前达到看门狗超时周期的情况下产生切换信号，其中切换电路打开第一数据总线开关并关闭第二数据总线开关响应切换信号。

3. 发明授权

US4908784A Method and apparatus for asynchronous time measurement 失效
标题翻译：用于异步时间测量的方法和装置
公开(公告)号：US4908784A
公开(公告)日：1990-03-13
申请号：US81368
申请日：1987-08-04
申请人： Gary W. Box , Thomas S. Foote-Lennox , Rodney G. Herreid , James F. Hoff , Dennis J. Leisz , John A. Perlick , Terry T. Steeden , John J. Turner , Curtis R. Alexander
发明人： Gary W. Box , Thomas S. Foote-Lennox , Rodney G. Herreid , James F. Hoff , Dennis J. Leisz , John A. Perlick , Terry T. Steeden , John J. Turner , Curtis R. Alexander
IPC分类号： G04F10/00 , G04F10/04
CPC分类号： G04F10/04 , G04F10/00
摘要： The present invention relates to time measurement apparatus and method for measuring, with picosecond precision, intervals between single edged events, where each measured interval comprises the summation of a rough clock count and fine or calibrated vernier counts of measured fractional clock periods before and after each START and STOP event selected from a calibrated vernier memory. The calibrated vernier memory takes the form of a table of linear voltage versus time developed using pseudo-random generated measurement events of random duration and random separation.
摘要翻译：本发明涉及时间测量装置和方法，用于以皮秒精度测量单边事件之间的间隔，其中每个测量间隔包括粗略时钟计数和每个测量之前和之后测量的分数时钟周期的精确或校准的游标计数的总和 START和STOP事件从校准的游标存储器中选择。校准的游标存储器采用随机持续时间和随机分离的伪随机生成测量事件形成的线性电压与时间表的形式。

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