专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5973966A Reading circuit for semiconductor memory cells 有权
标题翻译：半导体存储单元的读取电路
公开(公告)号：US5973966A
公开(公告)日：1999-10-26
申请号：US203798
申请日：1998-12-01
申请人： Cristiano Calligaro , Paolo Rolandi , Roberto Gastaldi , Guido Torelli
发明人： Cristiano Calligaro , Paolo Rolandi , Roberto Gastaldi , Guido Torelli
IPC分类号： G11C11/413 , G11C7/06 , G11C11/56 , G11C16/06 , G11C16/04
CPC分类号： G11C7/062 , G11C11/5621 , G11C11/5642 , G11C7/065 , G11C7/06
摘要： A read circuit for semiconductor memory cells, comprising first and second active elements coupled to a supply line via at least a first switch, wherein the first and second active elements are respectively connected, at first and second circuit nodes, respectively, to a first transistor through which the active elements are coupled to a ground. These first and second circuit nodes are also connected to ground through first and second capacitive elements, respectively, each having a switch connected in parallel to the capacitive element.
摘要翻译：一种用于半导体存储器单元的读取电路，包括经由至少第一开关耦合到电源线的第一和第二有源元件，其中第一和第二有源元件分别在第一和第二电路节点连接到第一晶体管有源元件通过它们耦合到地面。这些第一和第二电路节点分别通过第一和第二电容元件连接到地，每个具有与电容元件并联连接的开关。

2. 发明授权

US5883837A Reading circuit for semiconductor memory cells 失效
公开(公告)号：US5883837A
公开(公告)日：1999-03-16
申请号：US940115
申请日：1997-09-29
申请人： Cristiano Calligaro , Paolo Rolandi , Roberto Gastaldi , Guido Torelli
发明人： Cristiano Calligaro , Paolo Rolandi , Roberto Gastaldi , Guido Torelli
IPC分类号： G11C11/413 , G11C7/06 , G11C11/56 , G11C16/06 , G11C16/04
CPC分类号： G11C7/062 , G11C11/5621 , G11C11/5642 , G11C7/065 , G11C7/06
摘要： A read circuit for semiconductor memory cells, comprising first and second active elements coupled to a supply line via at least a first switch, wherein the first and second active elements are respectively connected, at first and second circuit nodes, respectively, to a first transistor through which the active elements are coupled to a ground. These first and second circuit nodes are also connected to ground through first and second capacitive elements, respectively, each having a switch connected in parallel to the capacitive element.

3. 发明授权

US5710739A Reading circuit for memory cells 失效
标题翻译：内存单元读取电路
公开(公告)号：US5710739A
公开(公告)日：1998-01-20
申请号：US476547
申请日：1995-06-06
申请人： Cristiano Calligaro , Roberto Gastaldi , Paolo Rolandi , Guido Torelli
发明人： Cristiano Calligaro , Roberto Gastaldi , Paolo Rolandi , Guido Torelli
IPC分类号： G11C11/419 , G11C7/06 , G11C7/00
CPC分类号： G11C7/065
摘要： A read circuit for memory cells which has two legs, each having, in cascade with one another, an electronic switch (SW1,SW2), an active element (T1,T2), feedback connected to the active element in the other leg to jointly produce a voltage amplifier, and a switch load element (L1,L2). Each active element is driven through a high-impedance input circuit element.
摘要翻译：一种用于存储单元的读取电路，其具有两个彼此级联的两条支路，一个电子开关（SW1，SW2），一个有源元件（T1，T2），与另一条支路中的有源元件连接的反馈产生电压放大器和开关负载元件（L1，L2）。每个有源元件通过高阻抗输入电路元件驱动。

4. 发明授权

US5999445A Multilevel non-volatile memory devices 失效
标题翻译：多级非易失性存储器件
公开(公告)号：US5999445A
公开(公告)日：1999-12-07
申请号：US916874
申请日：1997-08-22
申请人： Paolo Rolandi , Cristiano Calligaro , Alessandro Manstretta , Guido Torelli
发明人： Paolo Rolandi , Cristiano Calligaro , Alessandro Manstretta , Guido Torelli
IPC分类号： G11C16/02 , G11C11/56 , G11C11/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C16/102 , G11C2211/5621
摘要： In a storage device of the multi-level type, comprising a plurality of memory cells addressable through an address input each cell being adapted for storing more than one binary information element in a MOS transistor which has a control gate, and a floating gate for storing electrons to modify the threshold voltage of the transistor, and comprising a circuit enabling a Direct Memory Access (DMA) mode for directly accessing the memory cells from outside the device, the memory cells are programmed in the direct memory access mode by controlling, from outside the device, the amount of charge stored into the floating gate of each transistor.
摘要翻译：在多级类型的存储装置中，包括可通过地址输入寻址的多个存储器单元，每个单元适于在具有控制栅极的MOS晶体管中存储多于一个二进制信息元素，以及用于存储的浮动栅极电子来修改晶体管的阈值电压，并且包括能够直接存储器访问（DMA）模式的电路，用于从设备外部直接访问存储器单元，通过从外部控制来将存储器单元编程为直接存储器访问模式该器件，每个晶体管的浮置栅极存储的电荷量。

5. 发明授权

US6016271A Method and circuit for generating a gate voltage in non-volatile memory devices 有权
标题翻译：用于在非易失性存储器件中产生栅极电压的方法和电路
公开(公告)号：US6016271A
公开(公告)日：2000-01-18
申请号：US141250
申请日：1998-08-27
申请人： Paolo Rolandi , Roberto Gastaldi , Cristiano Calligaro
发明人： Paolo Rolandi , Roberto Gastaldi , Cristiano Calligaro
IPC分类号： G11C11/56 , G11C16/08 , G11C16/30 , G11C16/04
CPC分类号： G11C11/5642 , G11C11/5621 , G11C11/5628 , G11C16/08 , G11C16/30 , G11C2211/5634 , G11C29/00 , G11C8/14
摘要： A circuit generates a regulated voltage, in particular for gate terminals of non-volatile memory cells of the floating gate type. The circuit includes a generator circuit adapted to generate an unregulated voltage on its output. A comparator circuit is coupled to the output of the generator circuit including a reference element including a non-volatile memory cell of the floating gate type and adapted to output an error signal tied to the difference between the unregulated voltage and the threshold voltage of the cell. A regulator circuit is coupled to the output of the comparator circuit and is operative to regulate the unregulated voltage based on the value of the error signal. The regulated voltage is made programmable and tied to the parameters of the memory cell.
摘要翻译：电路产生调节电压，特别是对浮栅型非易失性存储单元的栅极端子。电路包括适于在其输出上产生未调节电压的发生器电路。比较器电路耦合到发生器电路的输出端，该输出包括一个参考元件，该参考元件包括一个浮动型的非易失性存储单元，并且适于输出一个与非稳态电压和该单元的阈值电压之间的差值相关的误差信号。调节器电路耦合到比较器电路的输出，并且可操作以基于误差信号的值来调节未调节的电压。调节电压是可编程的，并且与存储器单元的参数相关联。

6. 发明授权

US08759915B2 Semiconductor field-effect transistor, memory cell and memory device 有权
标题翻译：半导体场效应晶体管，存储单元和存储器件
公开(公告)号：US08759915B2
公开(公告)日：2014-06-24
申请号：US12293534
申请日：2006-03-20
申请人： Paolo Rolandi , Cristiano Calligaro , Luigi Pascucci
发明人： Paolo Rolandi , Cristiano Calligaro , Luigi Pascucci
IPC分类号： H01L21/02
CPC分类号： H01L27/11551 , H01L21/8221 , H01L27/0688 , H01L27/1052 , H01L27/115 , H01L27/1203 , H01L29/7832
摘要： Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.
摘要翻译：由半导体材料的第一导电条形成的半导体器件; 半导体材料的控制栅极区域，面对第一导电条的沟道部分，以及布置在第一导电条和控制栅极区域之间的绝缘区域。第一导电带包括具有第一导电类型的导线和具有彼此相邻并且彼此电接触布置的第二导电类型的控制线，并且导线形成沟道部分，第一导电部分和第二导电部分布置在通道部分的相对侧上。

7. 发明申请

US20100213529A1 SEMICONDUCTOR FIELD-EFFECT TRANSISTOR, MEMORY CELL AND MEMORY DEVICE 有权
标题翻译：半导体场效应晶体管，存储单元和存储器件
公开(公告)号：US20100213529A1
公开(公告)日：2010-08-26
申请号：US12293534
申请日：2006-03-20
申请人： Paolo Rolandi , Cristiano Calligaro , Luigi Pascucci
发明人： Paolo Rolandi , Cristiano Calligaro , Luigi Pascucci
IPC分类号： H01L29/788 , H01L21/28
CPC分类号： H01L27/11551 , H01L21/8221 , H01L27/0688 , H01L27/1052 , H01L27/115 , H01L27/1203 , H01L29/7832
摘要： Semiconductor device formed by a first conductive strip of semiconductor material; a control gate region of semiconductor material, facing a channel portion of the first conductive strip, and an insulation region arranged between the first conductive strip and the control gate region. The first conductive strip includes a conduction line having a first conductivity type and a control line having a second conductivity type, arranged adjacent and in electrical contact with each other, and the conduction line forms the channel portion, a first conduction portion and a second conduction portion arranged on opposite sides of the channel portion.
摘要翻译：由半导体材料的第一导电条形成的半导体器件; 半导体材料的控制栅极区域，面对第一导电条的沟道部分，以及布置在第一导电条和控制栅极区域之间的绝缘区域。第一导电带包括具有第一导电类型的导线和具有彼此相邻并且彼此电接触布置的第二导电类型的控制线，并且导线形成沟道部分，第一导电部分和第二导电部分布置在通道部分的相对侧上。

8. 发明授权

US5949666A Staircase adaptive voltage generator circuit 失效
标题翻译：楼梯自适应电压发生器电路
公开(公告)号：US5949666A
公开(公告)日：1999-09-07
申请号：US32282
申请日：1998-02-26
申请人： Vincenzo Daniele , Alessandro Manstretta , Paolo Rolandi , Guido Torelli
发明人： Vincenzo Daniele , Alessandro Manstretta , Paolo Rolandi , Guido Torelli
IPC分类号： G05F1/46 , H03K4/02 , H02M1/12 , G05F1/40 , G05F7/64
CPC分类号： G05F1/465 , H03K4/023
摘要： A staircase adaptive voltage generator circuit comprising a first capacitor connected between a first voltage reference and an output operational amplifier, through first and second switches, respectively. The terminals of the capacitor are also connected to a second voltage reference through third and fourth switches, respectively. A second capacitor, in series with a fifth switch, is connected in parallel to the first capacitor.
摘要翻译：一种楼梯自适应电压发生器电路，包括分别通过第一和第二开关连接在第一电压基准和输出运算放大器之间的第一电容器。电容器的端子也分别通过第三和第四开关连接到第二参考电压。与第五开关串联的第二电容器与第一电容器并联连接。

9. 发明授权

US06466479B2 Non-volatile memory matrix architecture with vertical insulation strips between adjacent memory blocks 有权
标题翻译：非易失性存储器矩阵结构，在相邻存储块之间具有垂直绝缘条
公开(公告)号：US06466479B2
公开(公告)日：2002-10-15
申请号：US09898744
申请日：2001-07-03
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C16/0491 , H01L27/115
摘要： A non-volatile memory matrix architecture, having a virtual ground monolithically integrated on a semiconductor substrate, includes a plurality of memory cells organized into matrix blocks. The matrix blocks are placed on rows and columns and are associated with respective row and column decoding circuits. The memory blocks are separated from each other by at least one insulation stripe which is parallel to the columns. The non-volatile memory matrix architecture further includes a pass-transistor decoding circuit with a number of levels corresponding to the number of rows to select.
摘要翻译：具有单片集成在半导体衬底上的虚拟接地的非易失性存储矩阵体系包括被组织成矩阵块的多个存储单元。矩阵块被放置在行和列上并且与相应的行和列解码电路相关联。存储块通过平行于列的至少一个绝缘条彼此分离。非易失性存储器矩阵架构还包括具有对应于要选择的行数的多个级别的传输晶体管解码电路。

10. 发明授权

US6097628A Multi-level memory circuit with regulated writing voltage 有权
标题翻译：具有稳压写电压的多电平存储电路
公开(公告)号：US6097628A
公开(公告)日：2000-08-01
申请号：US202656
申请日：1999-06-07
申请人： Paolo Rolandi
发明人： Paolo Rolandi
IPC分类号： G11C16/02 , G11C11/56 , G11C11/34
CPC分类号： G11C11/5621 , G11C11/5628 , G11C16/30 , G11C5/145
摘要： A multi-level memory circuit for binary information includes a plurality of memory cells each adapted to store more than one item of binary information, and each memory cell includes at least one floating gate MOS transistor. The information stored therein corresponds to the level of the cell threshold voltage. A write signal generating circuit is adapted to an input supply voltage and provides a write voltage to the memory cells. The write signal generating circuit generates internally at least one write voltage having a selectable or selected value from a number of discrete regulated values corresponding to the number of the discrete levels provided.
摘要翻译： PCT No.PCT / IT96 / 00199 Sec。 371日期1999年6月7日 102（e）1999年6月7日PCT PCT 1996年10月30日PCT公布。第WO97 / 49088号公报日期1997年12月24日用于二进制信息的多级存储器电路包括多个存储单元，每个存储单元适于存储多于一个二进制信息项，并且每个存储单元包括至少一个浮置栅极MOS晶体管。存储在其中的信息对应于单元阈值电压的电平。写入信号发生电路适于输入电源电压并向存储器单元提供写入电压。写入信号发生电路在内部产生至少一个写入电压，该写入电压具有与所提供的离散电平的数量相对应的多个离散调节值的可选择或选择的值。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式