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1. 发明授权

US08811453B2 Dynamic power scaling of an intermediate symbol buffer associated with covariance computations 有权
标题翻译：与协方差计算相关联的中间符号缓冲器的动态功率缩放
公开(公告)号：US08811453B2
公开(公告)日：2014-08-19
申请号：US13239586
申请日：2011-09-22
申请人： Ricky Nas , Cornelis Van Berkel , Jean-Paul Smeets
发明人： Ricky Nas , Cornelis Van Berkel , Jean-Paul Smeets
IPC分类号： H04B1/69 , H04B1/707 , H04B1/713 , H04B1/7115 , H04B1/7093
CPC分类号： H04B1/7115 , H04B2001/70935 , H04B2201/709727
摘要： An intermediate symbol buffer (ISB) configuration and method is provided such that the ISB memory comprises 15 portions, one for each HSDPA spreading code. Symbols associated with a spreading code are written to the memory portion associated with the same spreading code. When a covariance calculation is performed to obtain a more accurate channel estimate, only the symbols associated with spreading codes determined to be needed for the covariance calculation are written to the ISB by a buffer block and red from the ISB by a correlation core. The symbols associated with spreading codes that are not necessary for a covariance calculation may be masked from being written or read from the ISB. In some embodiments each memory portion is an individual memory block. In other embodiments a plurality of memory blocks may contain a plurality of memory portions, one memory partition designated, at least temporarily, for each spreading code.
摘要翻译：提供中间符号缓冲器（ISB）配置和方法，使得ISB存储器包括15个部分，每个HSDPA扩展码一个。与扩展码相关联的符号被写入与相同扩展码相关联的存储器部分。当执行协方差计算以获得更准确的信道估计时，只有与确定为协方差计算所需的扩展码相关联的符号由缓冲块写入ISB，并且通过相关核心从ISB写入红色。与协方差计算所不需要的扩展码相关联的符号可以从ISB中被写入或读取。在一些实施例中，每个存储器部分是单个存储器块。在其他实施例中，多个存储器块可以包含多个存储器部分，至少暂时为每个扩展码指定一个存储器分区。

2. 发明申请

US20130080711A1 DYNAMIC POWER SCALING OF AN INTERMEDIATE SYMBOL BUFFER ASSOCIATED WITH COVARIANCE COMPUTATIONS 有权
标题翻译：与协议计算相关的中间符号缓冲区的动态功率调整
公开(公告)号：US20130080711A1
公开(公告)日：2013-03-28
申请号：US13239586
申请日：2011-09-22
申请人： Ricky Nas , Cornelis Van Berkel , Jean-Paul Smeets
发明人： Ricky Nas , Cornelis Van Berkel , Jean-Paul Smeets
IPC分类号： G06F12/02
CPC分类号： H04B1/7115 , H04B2001/70935 , H04B2201/709727
摘要： An intermediate symbol buffer (ISB) configuration and method is provided such that the ISB memory comprises 15 portions, one for each HSDPA spreading code. Symbols associated with a spreading code are written to the memory portion associated with the same spreading code. When a covariance calculation is performed to obtain a more accurate channel estimate, only the symbols associated with spreading codes determined to be needed for the covariance calculation are written to the ISB by a buffer block and red from the ISB by a correlation core. The symbols associated with spreading codes that are not necessary for a covariance calculation may be masked from being written or read from the ISB. In some embodiments each memory portion is an individual memory block. In other embodiments a plurality of memory blocks may contain a plurality of memory portions, one memory partition designated, at least temporarily, for each spreading code.
摘要翻译：提供中间符号缓冲器（ISB）配置和方法，使得ISB存储器包括15个部分，每个HSDPA扩展码一个。与扩展码相关联的符号被写入与相同扩展码相关联的存储器部分。当执行协方差计算以获得更准确的信道估计时，只有与确定为协方差计算所需的扩展码相关联的符号由缓冲块写入ISB，并且通过相关核心从ISB写入红色。与协方差计算所不需要的扩展码相关联的符号可以从ISB中被写入或读取。在一些实施例中，每个存储器部分是单个存储器块。在其他实施例中，多个存储器块可以包含多个存储器部分，至少暂时为每个扩展码指定一个存储器分区。

3. 发明申请

US20060269037A1 Configurable multi-step linear feedback shift register 有权
标题翻译：可配置的多步线性反馈移位寄存器
公开(公告)号：US20060269037A1
公开(公告)日：2006-11-30
申请号：US10552048
申请日：2004-03-30
申请人： Cornelis Van Berkel , Ricky Nas
发明人： Cornelis Van Berkel , Ricky Nas
IPC分类号： G11C19/00
CPC分类号： G06F7/584 , G06F7/72
摘要： The state transition of a linear feedback shift register (LFSR) controlled by a clock (310) with length N and step size W, W being at least two, is accomplished via a next-state function (320). The next-state function deploys a state transition matrix (350). The state vector (330), which represents the contents of the LFSR, is either multiplied sequentially by the state transition matrix or multiplied by the state transition matrix to the power of W (multiple state transition matrix). The method and the LFSR according to the invention are characterized in that the multiple state transition matrix is decomposed in a first matrix (360) and a second matrix (370), the first matrix comprising at most N+W+1 different expressions and the second matrix comprising at most N+W+1 different expressions. The LFSR further comprises means to multiply the state vector by the second matrix and the first matrix, and means for computing the first matrix. The invention overcomes the shortcomings of configurable multi-step linear feedback shift registers because the amount of time needed to generate the output can be reduced significantly.
摘要翻译：通过下一状态功能（320）实现由具有长度N和步长W，W至少为2的时钟（310）控制的线性反馈移位寄存器（LFSR）的状态转换。下一状态函数部署状态转换矩阵（350）。代表LFSR的内容的状态向量（330）被状态转移矩阵顺序相乘或乘以状态转移矩阵到W的幂（多状态转移矩阵）。根据本发明的方法和LFSR的特征在于，多状态转移矩阵在第一矩阵（360）和第二矩阵（370）中被分解，第一矩阵包括至多N + W + 1个不同表达式，并且第二矩阵包括至多N + W + 1个不同表达式。 LFSR还包括将状态向量乘以第二矩阵和第一矩阵的装置，以及用于计算第一矩阵的装置。本发明克服了可配置的多级线性反馈移位寄存器的缺点，因为可以显着地减少产生输出所需的时间量。

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