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1. 发明授权

US4616339A Integrated circuit with improved programmable read-only memory 失效
标题翻译：具有改进的可编程只读存储器的集成电路
公开(公告)号：US4616339A
公开(公告)日：1986-10-07
申请号：US618006
申请日：1984-06-06
申请人： Roger Cuppens , Cornelis D. Hartgring
发明人： Roger Cuppens , Cornelis D. Hartgring
IPC分类号： G11C17/00 , G11C16/06 , G11C16/12 , G11C7/00
CPC分类号： G11C16/12
摘要： Field effect transistors having a short channel length are desirable for carrying out logic operations at a high speed. However, they are then not capable of withstanding the comparatively high programming and erasing voltage at which an (E)EPROM has to be operated. During the programming cycle the field effect transistors are kept in the current-nonconducting state, while recording the logic information obtained by the logic operations, the "fast" transistors are nevertheless capable of withstanding the comparatively high voltage.
摘要翻译：具有短信道长度的场效应晶体管对于高速执行逻辑运算是理想的。然而，它们不能承受必须操作（E）EPROM的相对较高的编程和擦除电压。在编程周期期间，场效应晶体管保持在电流 - 非导通状态，同时记录通过逻辑运算获得的逻辑信息，但是“快速”晶体管仍能承受较高的电压。

2. 发明授权

US5086331A Integrated circuit comprising a programmable cell 失效
标题翻译：包含可编程单元的集成电路
公开(公告)号：US5086331A
公开(公告)日：1992-02-04
申请号：US643687
申请日：1991-01-18
申请人： Cornelis D. Hartgring , Roger Cuppens
发明人： Cornelis D. Hartgring , Roger Cuppens
IPC分类号： G11C17/06 , G06K19/073 , G11C11/22 , G11C14/00 , G11C17/04 , H01L21/822 , H01L21/8247 , H01L27/04 , H01L27/115
CPC分类号： G11C17/04 , G11C11/22 , H01L27/115
摘要： The invention relates to an integrated circuit having a programmable cell, more particularly for use in an electronic card. The cell is provided with a programmable element (P) having two conductive layers (51, 52), which are separated from each other by a dielectric layer (53). The element can be programmed by applying between the layers 51, 52 a programming voltage such that an electric breakdown is produced in the dielectric layer (53), as a result of which the element passes permanently from an electrically non-conducting state to an electrically conducting state. According to the invention, the programmable cell comprises an asymmetric bistable trigger circuit (I,II). The trigger circuit (I,II) is loaded with the element (P) in such a manner that during operation it is in a first state if the element is electrically non-conducting and is in a second state if the element is electrically conducting.

3. 发明授权

US4707807A Non-volatile, programmable, static memory cell 失效
标题翻译：非易失性，可编程，静态存储单元
公开(公告)号：US4707807A
公开(公告)日：1987-11-17
申请号：US806313
申请日：1985-12-09
申请人： Roger Cuppens , Cornelis D. Hartgring
发明人： Roger Cuppens , Cornelis D. Hartgring
IPC分类号： G11C14/00 , G11C11/00
CPC分类号： G11C14/00
摘要： A memory and a non-volatile, programmable, static memory cell in which a programmable transistor and a capacitance are added to a known static memory cell. The cross-wise couplings between the transistors of the static cell form a first and a second junction. The gate and a main electrode (drain) of the programmable transistor are connected to the first junction. The second junction is connected to an injection location opposite the floating gate of the programmable transistor whose channel is connected in series with the capacitance the other side of which is connected to the sources of the two transistors of the static cell.
摘要翻译：存储器和非易失性，可编程的静态存储单元，其中可编程晶体管和电容被添加到已知的静态存储单元。静电单元的晶体管之间的交叉耦合形成第一和第二结。可编程晶体管的栅极和主电极（漏极）连接到第一结。第二结连接到与可编程晶体管的浮动栅极相对的注入位置，该可编程晶体管的沟道与其另一侧的静电电容的两个晶体管的源极连接的电容串联连接。

4. 发明授权

US4603402A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US4603402A
公开(公告)日：1986-07-29
申请号：US677639
申请日：1984-12-04
申请人： Roger Cuppens , Cornelis D. Hartgring
发明人： Roger Cuppens , Cornelis D. Hartgring
IPC分类号： G11C17/00 , G11C16/04 , G11C16/10 , G11C16/14 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , G11C11/40
CPC分类号： G11C16/10 , G11C16/14 , H01L29/7881 , H01L29/7883
摘要： The invention relates to an EPROM or an EEPROM in which the information is stored in the form of electrical charge above the channel region of a MOST, as a result of which the threshold voltage of the MOST is determined by the stored information. Writing/erasing of the memory generally requires high voltages to cause charge current to flow through an insulating layer to and from the charge storage region. In order to avoid having the parasitic MOSTs becoming conductive, means are provided by which during operation a small reverse bias is applied to the sources of these parasitic transistors, as a result of which due to the high k factor the threshold voltage of the parasitic transistors increases considerably. This does not require additional logic because use can be made of the generator in the reading circuit, which generates a suitable small voltage.
摘要翻译：本发明涉及一种EPROM或EEPROM，其中信息以MOST的信道区域上方的电荷形式存储，结果MOST的阈值电压由存储的信息确定。存储器的写入/擦除通常需要高电压以使充电电流通过电荷存储区域中的绝缘层流过绝缘层。为了避免使寄生MOST变得导通，提供了在操作期间向这些寄生晶体管的源极施加小的反向偏压的装置，其结果是由于高k因子，寄生晶体管的阈值电压大大增加这不需要额外的逻辑，因为可以在读取电路中使用发生器，从而产生合适的小电压。

5. 发明申请

US20060056223A1 Mram-cell and array-architecture with maximum read-out signal and reduced electromagnetic interference 有权
标题翻译：具有最大读出信号和降低电磁干扰的Mram-cell和阵列架构
公开(公告)号：US20060056223A1
公开(公告)日：2006-03-16
申请号：US10515475
申请日：2003-05-19
申请人： Anthonie Ditewig , Roger Cuppens
发明人： Anthonie Ditewig , Roger Cuppens
IPC分类号： G11C11/22
CPC分类号： G11C11/16 , G11C11/15
摘要： An MRAM memory is proposed which gives a maximum read-out signal. This is advantageous for high-speed sensing of the MRAM bits. In an MRAM memory with magnetoresistive memory cells linked together to form logically organized rows and columns, It is obtained by, at least during writing, connecting write bitlines of two adjacent rows or columns with each other, so as to write inverse data values in two adjacent memory cells. In this way, a return path for the writing current is provided in a small loop, which enhances EMC behavior.
摘要翻译：提出了一种提供最大读出信号的MRAM存储器。这对于MRAM位的高速感测是有利的。在具有连接在一起形成逻辑组织的行和列的磁阻存储器单元的MRAM存储器中，至少在写入期间通过将两个相邻行或列的写位线彼此连接来获得，以便将二进制数据值写入二相邻的存储单元。以这种方式，写入电流的返回路径以小环路提供，这增强了EMC行为。

6. 发明授权

US5879990A Semiconductor device having an embedded non-volatile memory and method of manufacturing such a semicondutor device 失效
标题翻译：具有嵌入式非易失性存储器的半导体器件和制造这种半导体器件的方法
公开(公告)号：US5879990A
公开(公告)日：1999-03-09
申请号：US814868
申请日：1997-03-11
申请人： Guido J. M. Dormans , Robertus D. J. Verhaar , Roger Cuppens
发明人： Guido J. M. Dormans , Robertus D. J. Verhaar , Roger Cuppens
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/43 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11526 , H01L27/105 , H01L27/11543 , H01L29/42324
摘要： The invention relates in particular, though not exclusively, to an integrated circuit with an embedded non-volatile memory with floating gate (10). According to the invention, at least two poly layers of equal or at least substantially equal thickness are used for this device. The first poly layer, poly A, is for the floating gate (10) and for the gates (22) of NMOS and PMOS in the logic portion of the circuit. The second poly layer, poly B, serves exclusively for the control electrode (21) above the floating gate. If so desired, a third poly layer may be deposited for both the control electrode and the logic gates, so that the thicknesses of these electrodes, and thus their resistances, are given desired values. Problems like overetching and bridging during saliciding are prevented in that the control electrode and the logic gates have the same thickness.
摘要翻译：本发明特别涉及具有带有浮动栅极（10）的嵌入式非易失性存储器的集成电路（尽管并非排他地）。根据本发明，对于该装置使用至少两个相等或至少基本相等厚度的多层。第一多晶硅层poly是用于浮置栅极（10）和电路的逻辑部分中的NMOS和PMOS的栅极（22）。第二多晶硅层poly B专门用于浮栅之上的控制电极（21）。如果需要，可以为控制电极和逻辑门两者沉积第三多晶硅层，使得这些电极的厚度以及因此它们的电阻被赋予所需的值。由于控制电极和逻辑门具有相同的厚度，所以防止了在浇注过程中过蚀刻和桥接的问题。

7. 发明授权

US4862418A Non-volatile, programmable semiconductor memory having reduced testing time 失效
标题翻译：非易失性，可编程半导体存储器具有缩短的测试时间
公开(公告)号：US4862418A
公开(公告)日：1989-08-29
申请号：US266346
申请日：1988-11-01
申请人： Roger Cuppens , Joannes J. M. Koomen
发明人： Roger Cuppens , Joannes J. M. Koomen
IPC分类号： H01L27/10 , G11C16/04 , G11C17/00 , G11C29/00 , G11C29/24
CPC分类号： G11C29/24
摘要： In programmable memories of the EPROM or EEPROM type, a row and/or column of test memory cells are added to the matrix of rows and columns of non-volatile memory cells for the testing of the peripheral circuits which select and read the memory cells. The test memory cells have a very short write time as compared with the non-volatile memory cells and may be of the dynamic (or volatile) type. The write time for a memory cell of the EPROM or EEPROM may be, for example, 10 msec. The write time for a dynamic memory cell, however, is 100 nsec. The time required for testing the peripheral circuits can therefore be reduced by a factor of 80 (for a 16 Kbit memory) or higher (for memories larger than 16 Kbits).
摘要翻译：在EPROM或EEPROM类型的可编程存储器中，测试存储器单元的行和/或列被添加到非易失性存储单元的行和列的矩阵中，用于测试选择和读取存储单元的外围电路。测试存储单元与非易失性存储单元相比具有非常短的写入时间，并且可以是动态（或易失性）类型。 EPROM或EEPROM的存储单元的写入时间可以是例如10毫秒。然而，动态存储单元的写入时间为100ns。因此，测试外围电路所需的时间可以降低80倍（对于16 Kbit存储器）或更高（对于大于16 Kbits的存储器）。

8. 发明授权

US07986548B2 Current re-routing scheme for serial-programmed MRAM 有权
标题翻译：串行编程MRAM的当前重路由方案
公开(公告)号：US07986548B2
公开(公告)日：2011-07-26
申请号：US10536271
申请日：2003-10-29
申请人： Anthonie Meindert Herman Ditewig , Roger Cuppens
发明人： Anthonie Meindert Herman Ditewig , Roger Cuppens
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： The present invention provides a method and device for programming a magnetic random access memory element with reduced current consumption, by re-routing digitline current through a selected bitline in a selected direction.
摘要翻译：本发明提供一种用于通过在所选方向上重新路由选定位线的数字线电流来编程具有降低的电流消耗的磁随机存取存储器元件的方法和装置。

9. 发明申请

US20060062067A1 Magnetoresistive memory cell array and mram memory comprising such array 有权
标题翻译：磁阻存储单元阵列和包含这种阵列的mram存储器
公开(公告)号：US20060062067A1
公开(公告)日：2006-03-23
申请号：US10515155
申请日：2003-05-16
申请人： Anthonie Ditewig , Roger Cuppens
发明人： Anthonie Ditewig , Roger Cuppens
IPC分类号： G11C7/00
CPC分类号： G11C11/16 , G11C8/16
摘要： The present invention describes a matrix with magnetoresistive memory cells arranged in logically organized rows and columns, Each memory cell includes a magnetoresistive element. The matrix comprises means for simultaneously reading from one cell in a column and writing to another cell in a column, or means for simultaneous reading from one cell in a row and writing to another cell in the same row. Such matrix can be used in a read-while-write MRAM memory.
摘要翻译：本发明描述了一种具有按逻辑组织的行和列布置的磁阻存储器单元的矩阵。每个存储单元包括磁阻元件。矩阵包括用于同时从列中的一个单元读取并写入列中的另一个单元的装置，或用于同时从一行中的一个单元读取并写入同一行中的另一单元的装置。这样的矩阵可以用在读写MRAM存储器中。

10. 发明授权

US5895950A Semiconductor device having a non-volatile memory and method of manufacturing such a semiconductor device 失效
标题翻译：具有非易失性存储器的半导体器件和制造这种半导体器件的方法
公开(公告)号：US5895950A
公开(公告)日：1999-04-20
申请号：US838247
申请日：1997-04-17
申请人： Andrew J. Walker , Roger Cuppens , Alwin N. Kronert
发明人： Andrew J. Walker , Roger Cuppens , Alwin N. Kronert
IPC分类号： H01L21/8247 , G11C16/16 , H01L27/105 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L29/7885 , G11C16/16 , H01L27/105 , H01L27/11526
摘要： The invention relates to a non-volatile memory with floating gate, in particular a Flash-EPROM, in which writing takes place through injection of hot electrons into the floating gate and in which erasing takes place through injection of hot holes. To keep the write and erase voltages sufficiently low, p-type zones which locally increase the background doping concentration of the p-type substrate are provided around the n-type source and drain zones. These p-type zones cause an increased field strength at the drain zone whereby hot electrons are formed at the pinch-off point also at lower voltages. This increased background concentration in addition reduces the breakdown voltage of the pn junction of the source and drain zones, so that hot holes for erasing can be formed by pn breakdown at comparatively low voltages. The device is particularly suitable for being integrated into a signal processing IC manufactured in a standard process, such as a microcontroller.
摘要翻译：本发明涉及一种具有浮动栅极，特别是闪存EPROM的非易失性存储器，其中通过将热电子注入到浮动栅极中进行写入，并且其中通过注入热孔进行擦除。为了保持写入和擦除电压足够低，在n型源极和漏极区域周围设置有局部增加p型衬底的背景掺杂浓度的p型区域。这些p型区域在漏极区域引起增加的场强，从而也在较低电压下在夹断点处形成热电子。此外，这种增加的背景浓度还降低了源区和漏区的pn结的击穿电压，从而可以通过在较低电压下的pn击穿来形成用于擦除的热孔。该器件特别适合于集成到诸如微控制器的标准处理中制造的信号处理IC中。

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