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1. 发明申请

US20060113524A1 Polymer-based transistor devices, methods, and systems 审中-公开
标题翻译：基于聚合物的晶体管器件，方法和系统
公开(公告)号：US20060113524A1
公开(公告)日：2006-06-01
申请号：US11000685
申请日：2004-12-01
申请人： Colin Bill , Michael Van Buskirk , Zhida Lan , John Ennals , Tzu-Ning Fang
发明人： Colin Bill , Michael Van Buskirk , Zhida Lan , John Ennals , Tzu-Ning Fang
IPC分类号： H01L29/08
CPC分类号： H01L51/102 , H01L51/0525
摘要： One aspect of the present invention relates to a semiconductor transistor device with an annular gate surrounding, at least in part, a channel that conducts current between a first and second source/drain. Another aspect of the present invention relates to a semiconductor transistor device having an annular gate and containing a channel composed of a polymer material. Yet another aspect of the present invention relates to fabrication of a device utilizing a polymer channel surrounded, at least in part, by an annular gate. Still yet another aspect of the present invention relates to a system with a means to control (and/or amplify) current via an annular gate surrounding a channel which conducts current between a first and second source/drain. Still other aspects of the present invention include devices incorporating the present invention's devices, systems and methods such as computers, memory, handhelds and electronic devices.
摘要翻译：本发明的一个方面涉及一种具有环形栅极的半导体晶体管器件，该环形栅极至少部分地包围在第一和第二源极/漏极之间传导电流的沟道。本发明的另一方面涉及一种具有环形栅极并且包含由聚合物材料构成的通道的半导体晶体管器件。本发明的另一方面涉及使用至少部分由环形栅极包围的聚合物通道的装置的制造。本发明的另一方面涉及一种具有通过围绕在第一和第二源极/漏极之间传导电流的沟道的环形栅极来控制（和/或放大）电流的装置的系统。本发明的其它方面包括结合本发明的装置，诸如计算机，存储器，手持设备和电子装置的系统和方法的装置。

2. 发明授权

US07273766B1 Variable density and variable persistent organic memory devices, methods, and fabrication 有权
标题翻译：可变密度和可变持久性有机存储器件，方法和制造
公开(公告)号：US07273766B1
公开(公告)日：2007-09-25
申请号：US11034071
申请日：2005-01-12
申请人： Zhida Lan , Michael A. Van Buskirk , Tzu-Ning Fang , Colin Bill , John S. Ennals
发明人： Zhida Lan , Michael A. Van Buskirk , Tzu-Ning Fang , Colin Bill , John S. Ennals
IPC分类号： H01L21/00
CPC分类号： H01L27/285 , G11C11/5664 , G11C13/0014 , G11C13/0016 , G11C13/0035 , G11C13/0061 , G11C13/0069 , G11C14/00 , G11C2213/55 , G11C2213/71
摘要： An organic memory device comprising two electrodes having a selectively conductive decay media between the two electrodes provides a capability to control a persistence level for information stored in an organic memory cell. A resistive state of the cell controls a conductive decay rate of the cell. A high and/or low resistive state can provide a fast and/or slow rate of conductive decay. One aspect of the present invention can have a high resistive state equating to an exponential conductive decay rate. Another aspect of the present invention can have a low resistive state equating to a logarithmic conductive decay rate. Yet another aspect relates to control of an organic memory device by determining a power state and setting a resistive state of an organic memory cell based upon a current power state and/or an imminent power state.
摘要翻译：包括在两个电极之间具有选择性导电衰减介质的两个电极的有机存储器件提供了控制存储在有机存储器单元中的信息的持久性水平的能力。电池的电阻状态控制电池的导电衰减速率。高和/或低电阻状态可以提供快速和/或慢速的导电衰减。本发明的一个方面可以具有等于指数导电衰减速率的高电阻状态。本发明的另一方面可以具有等于对数导电衰减速率的低电阻状态。另一方面涉及通过基于当前功率状态和/或迫在眉睫的功率状态确定有功存储器单元的功率状态和设置电阻状态来控制有机存储器件。

3. 发明授权

US06943370B2 Control of memory arrays utilizing zener diode-like devices 有权
标题翻译：使用齐纳二极管状器件来控制存储器阵列
公开(公告)号：US06943370B2
公开(公告)日：2005-09-13
申请号：US10882538
申请日：2004-06-30
申请人： Michael A. VanBuskirk , Colin Bill , Tzu-Ning Fang , Zhida Lan
发明人： Michael A. VanBuskirk , Colin Bill , Tzu-Ning Fang , Zhida Lan
IPC分类号： G11C11/56 , G11C13/02 , G11C16/02 , H01L51/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , G11C13/003 , G11C2213/71 , G11C2213/72 , G11C2213/77
摘要： The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.
摘要翻译：本发明通过帮助单个器件改变半导体阵列中的状态的方式来帮助半导体器件。可以将状态变化电压施加到半导体器件阵列中的单个器件，而不需要晶体管型电压控制。本发明的二极体效应通过允许状态改变所需的特定电压水平仅发生在期望的装置来促进该活动。以这种方式，可以在不利用晶体管技术的情况下用不同的数据或状态对器件阵列进行编程。本发明还允许制造这些类型的器件的非常有效的方法，消除了制造昂贵的外部电压控制半导体器件的需要。

4. 发明授权

US06847047B2 Methods that facilitate control of memory arrays utilizing zener diode-like devices 有权
标题翻译：方便使用齐纳二极管状器件来控制存储器阵列
公开(公告)号：US06847047B2
公开(公告)日：2005-01-25
申请号：US10287363
申请日：2002-11-04
申请人： Michael A. VanBuskirk , Colin Bill , Tzu-Ning Fang , Zhida Lan
发明人： Michael A. VanBuskirk , Colin Bill , Tzu-Ning Fang , Zhida Lan
IPC分类号： G11C11/56 , G11C13/02 , G11C16/02 , H01L51/00
CPC分类号： G11C13/0014 , B82Y10/00 , G11C11/5664 , G11C13/0016 , G11C13/003 , G11C2213/71 , G11C2213/72 , G11C2213/77
摘要： The present invention facilitates semiconductor devices by aiding the efficiency in the way individual devices change states in a semiconductor array. State change voltages can be applied to a single device in the array of semiconductor devices without the need for transistor-type voltage controls. The diodic effect of the present invention facilitates this activity by allowing specific voltage levels necessary for state changes to only occur at the desired device. In this manner, an array of devices can be programmed with varying data or states without utilizing transistor technology. The present invention also allows for an extremely efficient method of producing these types of devices, eliminating the need to manufacture costly external voltage controlling semiconductor devices.
摘要翻译：本发明通过帮助单个器件改变半导体阵列中的状态的方式来帮助半导体器件。可以将状态变化电压施加到半导体器件阵列中的单个器件，而不需要晶体管型电压控制。本发明的二极体效应通过允许状态改变所需的特定电压水平仅发生在期望的装置来促进该活动。以这种方式，可以在不利用晶体管技术的情况下用不同的数据或状态对器件阵列进行编程。本发明还允许制造这些类型的器件的非常有效的方法，消除了制造昂贵的外部电压控制半导体器件的需要。

5. 发明申请

US20060221713A1 Write-once read-many times memory 有权
标题翻译：一次写入多次内存
公开(公告)号：US20060221713A1
公开(公告)日：2006-10-05
申请号：US11095849
申请日：2005-03-31
申请人： Michael VanBuskirk , Colin Bill , Zhida Lan , Tzu-Ning Fang
发明人： Michael VanBuskirk , Colin Bill , Zhida Lan , Tzu-Ning Fang
IPC分类号： G11C7/10
CPC分类号： G11C13/0014 , B82Y10/00
摘要： A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy.
摘要翻译：一次写入多次存储器件由第一和第二电极，第一和第二电极之间的无源层以及第一和第二电极之间的有源层组成。通过从被动层提供带电物质到活性层来对存储器件进行编程。存储器件可以被编程为使编程的存储器件具有第一擦除激活能量。本方法为编程的存储器件提供大于第一擦除激活能量的第二擦除激活能量。

6. 发明申请

US20060067105A1 Control of memory devices possessing variable resistance characteristics 有权
标题翻译：具有可变电阻特性的存储器件的控制
公开(公告)号：US20060067105A1
公开(公告)日：2006-03-30
申请号：US10983919
申请日：2004-11-08
申请人： Tzu-Ning Fang , Michael Van Buskirk , Colin Bill
发明人： Tzu-Ning Fang , Michael Van Buskirk , Colin Bill
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C11/5664 , B82Y10/00 , G11C13/0014 , G11C13/0069 , G11C13/0097 , G11C2013/0071 , G11C2013/0078 , G11C2213/15 , G11C2213/79
摘要： Systems and methods employing at least one constant current source to facilitate programming of an organic memory cell and/or employing at least one constant voltage source to facilitate erasing of a memory device. The present invention is utilized in single memory cell devices and memory cell arrays. Employing a constant current source prevents current spikes during programming and allows accurate control of a memory cell's state during write cycles, independent of the cell's resistance. Employing a constant voltage source provides a stable load for memory cells during erase cycles and allows for accurate voltage control across the memory cell despite large dynamic changes in cell resistance during the process.
摘要翻译：采用至少一个恒定电流源的系统和方法促进有机存储器单元的编程和/或采用至少一个恒定电压源以便于擦除存储器件。本发明用于单个存储器单元装置和存储单元阵列。使用恒流源防止编程期间的电流尖峰，并允许在写周期期间精确控制存储单元的状态，而与电池的电阻无关。使用恒定电压源在擦除周期期间为存储器单元提供稳定的负载，并且允许跨过存储器单元的精确的电压控制，尽管在该过程中电池电阻的大的动态变化。

7. 发明授权

US08098521B2 Method of providing an erase activation energy of a memory device 有权
标题翻译：提供存储器件的擦除激活能的方法
公开(公告)号：US08098521B2
公开(公告)日：2012-01-17
申请号：US11095849
申请日：2005-03-31
申请人： Michael A. VanBuskirk , Colin S. Bill , Zhida Lan , Tzu-Ning Fang
发明人： Michael A. VanBuskirk , Colin S. Bill , Zhida Lan , Tzu-Ning Fang
IPC分类号： G11C11/34
CPC分类号： G11C13/0014 , B82Y10/00
摘要： A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy.
摘要翻译：一次写入多次存储器件由第一和第二电极，第一和第二电极之间的无源层以及第一和第二电极之间的有源层组成。通过从被动层提供带电物质到活性层来对存储器件进行编程。存储器件可以被编程为使编程的存储器件具有第一擦除激活能量。本方法为编程的存储器件提供大于第一擦除激活能量的第二擦除激活能量。

8. 发明申请

US20120092924A1 METHOD OF PROVIDING AN ERASE ACTIVATION ENERGY OF A MEMORY DEVICE 审中-公开
标题翻译：提供存储器件的擦除活化能的方法
公开(公告)号：US20120092924A1
公开(公告)日：2012-04-19
申请号：US13324310
申请日：2011-12-13
申请人： Michael A. VanBuskirk , Colin S. Bill , Zhida Lan , Tzu-Ning Fang
发明人： Michael A. VanBuskirk , Colin S. Bill , Zhida Lan , Tzu-Ning Fang
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C13/0014 , B82Y10/00
摘要： A write-once read-many times memory device is made up of first and second electrodes, a passive layer between the first and second electrodes, and an active layer between the first and second electrode. The memory device is programmed by providing a charged species from the passive layer into the active layer. The memory device may be programmed to have for the programmed memory device a first erase activation energy. The present method provides for the programmed memory device a second erase activation energy greater than the first erase activation energy.
摘要翻译：一次写入多次存储器件由第一和第二电极，第一和第二电极之间的无源层以及第一和第二电极之间的有源层组成。通过从被动层提供带电物质到活性层来对存储器件进行编程。存储器件可以被编程为使编程的存储器件具有第一擦除激活能量。本方法为编程的存储器件提供大于第一擦除激活能量的第二擦除激活能量。

9. 发明申请

US20060139994A1 Method of programming, reading and erasing memory-diode in a memory-diode array 有权
标题翻译：在存储二极管阵列中编程，读取和擦除存储二极管的方法
公开(公告)号：US20060139994A1
公开(公告)日：2006-06-29
申请号：US11021958
申请日：2004-12-23
申请人： Colin Bill , Swaroop Kaza , Tzu-Ning Fang , Stuart Spitzer
发明人： Colin Bill , Swaroop Kaza , Tzu-Ning Fang , Stuart Spitzer
IPC分类号： G11C11/36
CPC分类号： G11C11/36
摘要： A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.
摘要翻译：存储器阵列包括第一和第二组导体和多个存储器二极管，每个存储器二极管以正向方向连接第一组的导体与第二组的导体。在选定的存储器二极管上施加电位，从正向上的较高电位到较低的电位，用于对所选存储二极管进行编程。在该期望的编程期间，阵列中的每个其它存储器二极管在其正向方向上提供低于其阈值电压的电位。每个存储器二极管的阈值电压可以通过在该存储器二极管上从相反方向上从较高电位向较低电位施加电位来建立。通过这样建立足够的阈值电压，并且通过选择适用于阵列导体的适当电位，避免了与电流泄漏和干扰有关的问题。

10. 发明申请

US20060104111A1 DIODE ARRAY ARCHITECTURE FOR ADDRESSING NANOSCALE RESISTIVE MEMORY ARRAYS 有权
标题翻译：用于解决纳米电阻记忆阵列的二极体阵列
公开(公告)号：US20060104111A1
公开(公告)日：2006-05-18
申请号：US10990706
申请日：2004-11-17
申请人： Nicholas Tripsas , Colin Bill , Michael VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Cai , Suzette Pangrle , Steven Avanzino
发明人： Nicholas Tripsas , Colin Bill , Michael VanBuskirk , Matthew Buynoski , Tzu-Ning Fang , Wei Cai , Suzette Pangrle , Steven Avanzino
IPC分类号： G11C11/36
CPC分类号： G11C13/003 , G11C13/0002 , G11C13/0007 , G11C2213/56 , G11C2213/72 , G11C2213/74 , G11C2213/76 , H01L27/101 , H01L27/1021
摘要： The present memory structure includes thereof a first conductor, a second conductor, a resistive memory cell connected to the second conductor, a first diode connected to the resistive memory cell and the first conductor, and oriented in the forward direction from the resistive memory cell to the first conductor, and a second diode connected to the resistive memory cell and the first conductor, in parallel with the first diode, and oriented in the reverse direction from the resistive memory cell to the first conductor. The first and second diodes have different threshold voltages
摘要翻译：本存储器结构包括第一导体，第二导体，连接到第二导体的电阻性存储单元，连接到电阻存储单元和第一导体的第一二极管，并且从电阻存储单元向前取向所述第一导体和连接到所述电阻性存储器单元和所述第一导体的第二二极管与所述第一二极管并联，并且在从所述电阻存储器单元到所述第一导体的相反方向上定向。第一和第二二极管具有不同的阈值电压

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