会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Control circuit with a level shifter for switching an electronic switch
    • 具有用于切换电子开关的电平转换器的控制电路
    • US5572156A
    • 1996-11-05
    • US529883
    • 1995-09-18
    • Claudio DiazziFabrizio MartignoniMario Tarantola
    • Claudio DiazziFabrizio MartignoniMario Tarantola
    • H02P7/29H03K3/356H03K17/06H03K17/16H03K17/687H03K3/00
    • H03K3/356113H03K17/063H03K17/161H03K17/687
    • A control circuit for a power transistor, connected between two supply terminals in series with a load. The control circuit comprises a control logic circuit which produces a signal at two levels with respect to a reference terminal, a level shifter connected between the control circuit and the power transistor, which produces a signal at two levels relative to the node between the power transistor and the load. The level shifter comprises a flip-flop the output of which controls the power transistor, and an electronic switch, for example a MOSFET transistor, connected between the "set" input of the flip-flop and the node and controlled by the "reset" input of the flip-flop in such a way as to be closed when the "reset" input is greater, by a predetermined value, than that of the node. The electronic switch prevents the parasitic current flowing through the set and reset inputs from erroneously switching the power transistor.
    • 用于功率晶体管的控制电路,连接在与负载串联的两个电源端子之间。 该控制电路包括控制逻辑电路,该控制逻辑电路相对于参考端产生两个电平的信号,连接在控制电路和功率晶体管之间的电平转换器,其产生相对于功率晶体管 和负载。 电平移位器包括其输出端控制功率晶体管的触发器和连接在触发器的“设置”输入和节点之间并由“复位”控制的电子开关,例如MOSFET晶体管, 触发器的输入以当“复位”输入比节点的输入大一预定值时被关闭。 电子开关防止流过设定和复位输入的寄生电流错误地切换功率晶体管。
    • 2. 发明授权
    • Charging of a bootstrap capacitance through an LDMOS
    • 通过LDMOS充电自举电容
    • US5883547A
    • 1999-03-16
    • US644449
    • 1996-05-13
    • Claudio DiazziFabrizio MartignoniMario Tarantola
    • Claudio DiazziFabrizio MartignoniMario Tarantola
    • G01R19/165H01L21/8234H01L27/088H02J1/00H03K17/06H03K17/0814H02M7/162
    • H03K17/08142H03K17/063
    • A charging circuit for a bootstrap capacitance employing an integrated LDMOS transistor and including a circuital device for preventing the turning on a parasitic transistors of the integrated LDMOS structure during transients that comprises a plurality of directly biased junctions (D1, D2, . . . , Dn) connected in series between a source and a body of the LDMOS transistor structure and at least a current generator, tied to ground potential, coupled between said body and ground, has at least one switch (INT1) between said source and a first junction (D1) of said plurality of junctions and a limiting resistance (R) connected between the body and the current generator (GEN). The switch (INT1) is kept open during a charging phase of the bootstrap capacitance (Cboot) and is closed when the charge voltage (Vboot) of the bootstrap capacitance reaches a preset threshold. Moreover, the body voltage (VB) is prevented from exceeding the source voltage (VS) plus a Vbe, by controlling a discharge path (T2) with a control stage (T1, R1) in response to a drop of the voltage on the limiting resistance (R). This body voltage control circuit is enabled by a second switch (INT2) driven in phase with the first switch (INT1).
    • 一种用于使用集成LDMOS晶体管的自举电容的充电电路,并且包括用于在包括多个直接偏置的结(D1,D2,...,Dn)的瞬变期间阻止集成LDMOS结构的寄生晶体管的导通的电路装置 )串联连接在LDMOS晶体管结构的源极和主体之间,并且至少连接在所述主体和地之间的接地电位的电流发生器在所述源和第一结之间具有至少一个开关(INT1) D1)和连接在主体和电流发生器(GEN)之间的限制电阻(R)。 开关(INT1)在自举电容(Cboot)的充电阶段保持打开,当自举电容的充电电压(Vboot)达到预设阈值时,开关闭合。 此外,通过响应于限制电压的下降控制具有控制级(T1,R1)的放电路径(T2),防止体电压(VB)超过源极电压(VS)加上Vbe 电阻(R)。 该体电压控制电路由与第一开关(INT1)同相驱动的第二开关(INT2)使能。
    • 4. 发明授权
    • Integrated control circuit with a level shifter for switching an
electronic switch
    • 具有用于切换电子开关的电平转换器的集成控制电路
    • US5552731A
    • 1996-09-03
    • US529882
    • 1995-09-18
    • Claudio DiazziFabrizio MartignoniMario Tarantola
    • Claudio DiazziFabrizio MartignoniMario Tarantola
    • H02P7/29H03K17/16H03K17/687H03K3/00
    • H03K17/687H03K17/161
    • A circuit for controlling a power transistor connected in series with a load. The circuit comprises a control logic circuit which produces a signal at two levels with respect to a reference terminal, a level shifter connected between the control circuit and the power transistor, and which produces a signal at two levels referred to the node between the power transistor and the load. The level shifter includes a flip-flop the output of which controls the power transistor as well as two transistors driven by the control logic circuit to switch alternately and provide switching signals on the "set" and "reset" inputs of the flip-flop via two resistors. Two parasitic current generators inject current into the two resistors during the phase in which the power transistor is cut off. To prevent this current from causing unwanted switching of the flip-flop, a resistor connected to the "set" terminal of the flip-flop has a lower resistance than that of the other resistor.
    • 用于控制与负载串联连接的功率晶体管的电路。 该电路包括控制逻辑电路,该控制逻辑电路相对于参考端产生两个电平的信号,连接在控制电路和功率晶体管之间的电平转换器,并且其产生两个电平的信号,所述两个电平参考功率晶体管 和负载。 电平移位器包括触发器,其输出控制功率晶体管以及由控制逻辑电路驱动的两个晶体管交替切换,并在触发器的“设置”和“复位”输入端经由 两个电阻。 在功率晶体管截止的阶段,两个寄生电流发生器将电流注入到两个电阻中。 为了防止该电流引起触发器的不期望的切换,连接到触发器的“设置”端子的电阻器具有比另一个电阻器更低的电阻。