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    • 8. 发明授权
    • Updating high speed parallel I/O interfaces based on counters
    • 基于计数器更新高速并行I / O接口
    • US07062688B2
    • 2006-06-13
    • US10196384
    • 2002-07-16
    • Claude R. GauthierAninda K. RoyBrian W. AmickDean Liu
    • Claude R. GauthierAninda K. RoyBrian W. AmickDean Liu
    • G01R31/28
    • G06F11/24
    • A technique for adjusting a communication system involves a link, where the link includes a data line arranged to transmit a data signal and a clock line adapted to transmit a clock signal. The technique uses one or more counters to test the transmission across the link. Dependent on one or more of these counters, a test circuit, connected to the link, compares a known test pattern signal to a latched test pattern signal transmitted on the data line. The test circuit includes an adjustment circuit arranged to generate an adjustable clock signal from the clock signal, where the adjustable clock signal determines when to latch the transmitted test pattern signal The test circuit adjusts a timing of the adjustable clock signal relative to the data signal of the link.
    • 用于调整通信系统的技术涉及链路,其中链路包括被布置为发送数据信号的数据线和适于发送时钟信号的时钟线。 该技术使用一个或多个计数器来测试链路上的传输。 根据一个或多个这些计数器,连接到链路的测试电路将已知的测试模式信号与在数据线上发送的锁存的测试模式信号进行比较。 该测试电路包括调整电路,该调整电路被布置成从时钟信号产生可调节的时钟信号,其中可调节时钟信号确定何时锁存发送的测试图形信号。测试电路相对于数据信号的数据信号调整可调节时钟信号的定时 链接。