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1. 发明授权

US07474662B2 Systems and methods for rate-limited weighted best effort scheduling 失效
标题翻译：速率限制加权最佳努力调度的系统和方法
公开(公告)号：US07474662B2
公开(公告)日：2009-01-06
申请号：US11119329
申请日：2005-04-29
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L47/623 , H04L47/50 , H04L47/568
摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a four-entry calendar structure provides for rate-limited weighted best effort scheduling. Each of a plurality of different flows has associated schedule control blocks. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a rate limit according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its rate limit, the schedule control block is temporarily removed from further scheduling until a time interval concludes.
摘要翻译：公开了一种用于在网络处理器中调度数据分组的系统和方法。实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。在一个实施例中，四入口日历结构提供速率受限加权最佳努力调度。多个不同流中的每一个都具有相关联的调度控制块。计划控制块作为链表存储在先进先出缓冲区中。通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。每个调度控制块都有一个计数器，并根据相应数据包所属的流的带宽优先级分配速率限制。每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。当调度控制块的递增计数器等于其速率限制时，调度控制块暂时从进一步调度中移除，直到时间间隔结束。

2. 发明授权

US07409520B2 Systems and methods for time division multiplex multithreading 失效
标题翻译：时分复用多线程的系统和方法
公开(公告)号：US07409520B2
公开(公告)日：2008-08-05
申请号：US11042692
申请日：2005-01-25
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译：公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。如果要选择的线程无法执行，则选择补充线程执行。

3. 发明申请

US20080147995A1 SYSTEMS AND METHODS FOR MULTI-FRAME CONTROL BLOCKS 有权
标题翻译：多框控制块的系统和方法
公开(公告)号：US20080147995A1
公开(公告)日：2008-06-19
申请号：US12039304
申请日：2008-02-28
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
IPC分类号： G06F12/00
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.
摘要翻译：公开了一种用于在网络处理器中实现多帧控制块的系统和方法。实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

4. 发明授权

US07606166B2 System and method for computing a blind checksum in a host ethernet adapter (HEA) 失效
标题翻译：用于计算主机以太网适配器（HEA）中的盲校验和的系统和方法
公开(公告)号：US07606166B2
公开(公告)日：2009-10-20
申请号：US11097430
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
IPC分类号： H04L12/66
CPC分类号： H04L69/16 , H04L69/161
摘要： A system and method for computing a blind checksum includes a host Ethernet adapter (HEA) with a system for receiving a packet. The system determines whether or not the packet is in Internet protocol version four (IPv4). If the packet is not in IPv4, the system computes the checksum of the packet. If the packet is in IPv4, the system determines whether the packet is in transmission control protocol (TCP) or user datagram protocol (UDP). If the packet is not in either of TCP or UDP the system attaches a pseudo-header to the packet and computes the checksum of the packet based on the pseudo-header and the IPv4 standard.
摘要翻译：用于计算盲校验和的系统和方法包括具有用于接收分组的系统的主机以太网适配器（HEA）。系统确定数据包是否处于Internet协议版本四（IPv4）中。如果分组不在IPv4中，则系统计算分组的校验和。如果分组在IPv4中，则系统确定分组是否在传输控制协议（TCP）或用户数据报协议（UDP）中。如果分组不在TCP或UDP中，则系统将伪报头附加到分组，并基于伪报头和IPv4标准计算分组的校验和。

5. 发明授权

US07508771B2 Method for reducing latency in a host ethernet adapter (HEA) 失效
标题翻译：用于减少主机以太网适配器（HEA）中的延迟的方法
公开(公告)号：US07508771B2
公开(公告)日：2009-03-24
申请号：US11096353
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： H04L12/26
CPC分类号： H04L12/413 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/22 , H04L69/324
摘要： A method for reducing latency in a host Ethernet adapter (HEA) includes the following. First, the HEA receives a packet with an internet protocol (IP) header and data in the HEA. The HEA parses a connection identifier from the IP header and accesses a negative cache in the HEA to determine if the connection identifier is not in a memory external to the HEA. The HEA applies a default treatment to the packet if the connection identifier is not in the memory, thereby reducing latency by decreasing access to the memory.
摘要翻译：一种用于减少主机以太网适配器（HEA）中的延迟的方法包括以下。首先，HEA在HEA中接收到具有互联网协议（IP）头部和数据的分组。 HEA从IP头解析连接标识符，并访问HEA中的负缓存，以确定连接标识符是否不在HEA外部的存储器中。如果连接标识符不在存储器中，则HEA对数据包应用默认处理，从而通过减少对存储器的访问来减少延迟。

6. 发明授权

US07492771B2 Method for performing a packet header lookup 失效
标题翻译：执行分组报头查找的方法
公开(公告)号：US07492771B2
公开(公告)日：2009-02-17
申请号：US11096362
申请日：2005-04-01
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Ronald Edward Fuhs , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli , Scott Michael Willenborg
IPC分类号： H04L12/56
CPC分类号： H04L49/3009 , H04L45/742 , H04L49/25
摘要： A method for performing a lookup for a packet in a computer network are disclosed. The packet includes a header. The method includes providing a parser, providing a lookup engine coupled with the parser, and providing a processor coupled with the lookup engine. The parser is for parsing the packet for the header prior to receipt of the packet being completed. The lookup engine performs a lookup for the header and returns a resultant. In one aspect, the lookup includes performing a local lookup of a cache that includes resultants of previous lookups. The processor processes the resultant.
摘要翻译：公开了一种用于在计算机网络中执行查找分组的方法。分组包括报头。该方法包括提供解析器，提供与解析器耦合的查找引擎，以及提供与查找引擎耦合的处理器。解析器用于在接收到完成的数据包之前解析报头的数据包。查找引擎对标题执行查找并返回结果。在一个方面，查找包括执行包括先前查找的结果的高速缓存的本地查找。处理器处理结果。

7. 发明授权

US07376809B2 Systems and methods for multi-frame control blocks 有权
标题翻译：多帧控制块的系统和方法
公开(公告)号：US07376809B2
公开(公告)日：2008-05-20
申请号：US11076218
申请日：2005-03-09
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
IPC分类号： G06F12/02
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.
摘要翻译：公开了一种用于在网络处理器中实现多帧控制块的系统和方法。实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

8. 发明授权

US07529224B2 Scheduler, network processor, and methods for weighted best effort scheduling 失效
标题翻译：调度器，网络处理器和加权最佳努力调度的方法
公开(公告)号：US07529224B2
公开(公告)日：2009-05-05
申请号：US11108485
申请日：2005-04-18
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Natarajan Vaidhyanathan , Fabrice Jean Verplanken
IPC分类号： H04L12/28
CPC分类号： H04L47/568 , H04L45/00 , H04L45/60 , H04L47/50 , H04L47/527
摘要： Systems and methods for scheduling data packets in a network processor are disclosed. Embodiments provide a network processor that comprises a best-effort scheduler with a minimal calendar structure for addressing schedule control blocks. In one embodiment, a three-entry calendar structure provides for weighted best effort scheduling. Each of a plurality different flows has an associated schedule control block. Schedule control blocks are stored as linked lists in a last-in-first-out buffer. Each calendar entry is associated with a different linked list by storing in the calendar entry the address of the first-out schedule control block in the linked list. Each schedule control block has a counter and is assigned a weight according to the bandwidth priority of the flow to which the corresponding packet belongs. Each time a schedule control block is accessed from a last-in-first-out buffer storing the linked list, the scheduler generates a scheduling event and the counter of the schedule control block is incremented. When an incremented counter of a schedule control block equals its weight, the schedule control block is temporarily removed from further scheduling.
摘要翻译：公开了一种用于在网络处理器中调度数据分组的系统和方法。实施例提供了一种网络处理器，其包括具有用于寻址日程控制块的最小日历结构的尽力而为调度器。在一个实施例中，三入口日历结构提供加权最佳努力调度。多个不同的流中的每一个具有相关的进度控制块。计划控制块作为链表存储在先进先出缓冲区中。通过在日历条目中存储链表中的先出时间表控制块的地址来将每个日历条目与不同的链表相关联。每个调度控制块具有计数器，并根据相应分组所属的流的带宽优先级分配权重。每当从存储链表的最先进先出缓冲器访问调度控制块时，调度器生成调度事件，并且调度控制块的计数器递增。当调度控制块的递增计数器等于其权重时，调度控制块暂时从进一步调度中移除。

9. 发明申请

US20080317027A1 SYSTEM FOR REDUCING LATENCY IN A HOST ETHERNET ADAPTER (HEA) 审中-公开
标题翻译：用于减少主机以太网适配器（HEA）中的延迟的系统
公开(公告)号：US20080317027A1
公开(公告)日：2008-12-25
申请号：US12200970
申请日：2008-08-29
申请人： Claude BASSO , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude BASSO , Jean Louis Calvignac , Chih-jen Chang , Philippe Damon , Natarajan Vaidhyanathan , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： H04L12/56 , H04L12/28
CPC分类号： H04L12/413 , H04L69/12 , H04L69/16 , H04L69/161 , H04L69/22 , H04L69/324
摘要： A system for reducing latency in a host Ethernet adapter (HEA) includes the following. First, the HEA receives a packet with an internet protocol (IP) header and data in the HEA. The HEA parses a connection identifier from the IP header and accesses a negative cache in the HEA to determine if the connection identifier is not in a memory external to the HEA. The HEA applies a default treatment to the packet if the connection identifier is not in the memory, thereby reducing latency by decreasing access to the memory.
摘要翻译：用于减少主机以太网适配器（HEA）中的延迟的系统包括以下内容。首先，HEA在HEA中接收到具有互联网协议（IP）头部和数据的分组。 HEA从IP头解析连接标识符，并访问HEA中的负缓存，以确定连接标识符是否不在HEA外部的存储器中。如果连接标识符不在存储器中，则HEA对数据包应用默认处理，从而通过减少对存储器的访问来减少延迟。

10. 发明授权

US07953951B2 Systems and methods for time division multiplex multithreading 失效
标题翻译：时分复用多线程的系统和方法
公开(公告)号：US07953951B2
公开(公告)日：2011-05-31
申请号：US12124396
申请日：2008-05-21
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Gordon Taylor Davis , Harm Peter Hofstee , Fabrice Jean Verplanken , Colin Beaton Verrilli
IPC分类号： G06F12/00
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/4843
摘要： Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.
摘要翻译：公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。如果要选择的线程无法执行，则选择补充线程执行。

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