会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明授权
    • Level shifting circuit
    • 电平转换电路
    • US07768336B2
    • 2010-08-03
    • US12208056
    • 2008-09-10
    • Chung-hee KimMin-su KimJin-soo Park
    • Chung-hee KimMin-su KimJin-soo Park
    • H03L5/00
    • H03K19/00323H03K19/0016H03K19/018528
    • A level shifting circuit includes a first level shifting unit including a plurality of signal transfer units; a first operation control unit inactivating some of signal transfer units of the first level shifting unit in response to a clamping signal; a second level shifting unit connected in parallel to the first level shifting unit and comprising a plurality of signal transfer units; a second operation control unit inactivating some of signal transfer units of the second level shifting unit in response to the clamping signal; a signal output unit connected to output ends of the first and second level shifting units; and a clamping unit fixing the output ends of the first and second level shifting units to a predetermined voltage level in response to the clamping signal.
    • 电平移位电路包括:包括多个信号传送单元的第一电平移位单元; 第一操作控制单元响应于钳位信号而使第一电平移位单元的一些信号传送单元失活; 与第一电平移位单元并联连接并包括多个信号传送单元的第二电平移位单元; 第二操作控制单元响应于所述钳位信号而使所述第二电平移位单元的一些信号传送单元失活; 连接到第一和第二电平移动单元的输出端的信号输出单元; 以及夹紧单元,其响应于所述夹紧信号将所述第一和第二电平移位单元的输出端固定到预定电压电平。
    • 4. 发明申请
    • LEVEL SHIFTING CIRCUIT
    • 水平移位电路
    • US20090201069A1
    • 2009-08-13
    • US12208056
    • 2008-09-10
    • Chung-hee KimMin-su KimJin-soo Park
    • Chung-hee KimMin-su KimJin-soo Park
    • H03L5/00
    • H03K19/00323H03K19/0016H03K19/018528
    • A level shifting circuit includes a first level shifting unit including a plurality of signal transfer units; a first operation control unit inactivating some of signal transfer units of the first level shifting unit in response to a clamping signal; a second level shifting unit connected in parallel to the first level shifting unit and comprising a plurality of signal transfer units; a second operation control unit inactivating some of signal transfer units of the second level shifting unit in response to the clamping signal; a signal output unit connected to output ends of the first and second level shifting units; and a clamping unit fixing the output ends of the first and second level shifting units to a predetermined voltage level in response to the clamping signal.
    • 电平移位电路包括:包括多个信号传送单元的第一电平移位单元; 第一操作控制单元响应于钳位信号而使第一电平移位单元的一些信号传送单元失活; 与第一电平移位单元并联连接并包括多个信号传送单元的第二电平移位单元; 第二操作控制单元响应于所述钳位信号而使所述第二电平移位单元的一些信号传送单元失活; 连接到第一和第二电平移动单元的输出端的信号输出单元; 以及夹紧单元,其响应于所述夹紧信号将所述第一和第二电平移位单元的输出端固定到预定电压电平。
    • 5. 发明授权
    • Sense amplifier having synchronous reset or asynchronous reset capability
    • 具有同步复位或异步复位功能的感应放大器
    • US06972601B2
    • 2005-12-06
    • US10627855
    • 2003-07-25
    • Min-su Kim
    • Min-su Kim
    • G01R19/00G11C7/06H03F3/45H03K3/356
    • H03K3/356191G11C7/062H03K3/356182
    • A sense amplifier having a synchronous reset capability or an asynchronous reset capability, which is readily implemented and has high speed, is provided. The sense amplifier includes a first sense-amplifying unit which sense-amplifies an input signal in response to a clock signal and generates an output signal, and a second sense-amplifying unit which sense-amplifies a complementary signal of the input signal in response to the clock signal and generates a complementary signal of the output signal. The sense amplifier further includes a first controller which is connected to the first sense-amplifying unit and sets the output signal in response to a reset signal and an inverted signal of the reset signal, and a second controller which is connected to the second sense-amplifying unit and resets the complementary signal of the output signal in response to the reset signal and the inverted signal of the reset signal.
    • 提供具有同步复位能力或异步复位能力的读出放大器,其易于实现并且具有高速度。 感测放大器包括:第一感测放大单元,其响应于时钟信号来感测放大输入信号并产生输出信号;以及第二感测放大单元,其响应于所述输入信号而对输入信号的互补信号进行感测放大 时钟信号并产生输出信号的互补信号。 感测放大器还包括第一控制器,其连接到第一感测放大单元,并且响应于复位信号和复位信号的反相信号设置输出信号;以及第二控制器,其连接到第二感测放大单元, 放大单元,并且响应于复位信号和复位信号的反相信号复位输出信号的互补信号。
    • 6. 发明申请
    • High speed flip-flops and complex gates using the same
    • 高速触发器和使用相同的复合门
    • US20050225372A1
    • 2005-10-13
    • US11095187
    • 2005-03-31
    • Min-su Kim
    • Min-su Kim
    • H03K3/3562H03K3/012H03K3/037H03K3/289H03K3/356H03K5/1532H03K19/096H03K19/20
    • H03K3/012H03K3/356121H03K3/356191H03K19/20
    • In high-speed flip-flops and complex gates using the same, the flip-flop includes a first PMOS transistor and second and third NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the first PMOS transistor and the second NMOS transistor are connected to input data. A gate of the third NMOS transistor is connected to a clock pulse signal. A logic level of a first intermediate node between the first PMOS transistor and the second NMOS transistor is latched by a first latch. The flip-flop further includes a fourth PMOS transistor and fifth and sixth NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the fourth PMOS transistor and the fifth NMOS transistor are connected to the first intermediate node. A gate of the sixth NMOS transistor is connected to the clock pulse signal. A logic level of a second intermediate node between the fourth PMOS transistor and the fifth NMOS transistor is latched by a second latch. Accordingly, intermediate nodes of the flip-flops are connected to ground voltages via two NMOS transistors upon logic level switching, rather than three or more, so that the switching time of the device is shortened.
    • 在使用其的高速触发器和复合栅极中,触发器包括串联连接在电源电压和接地电压之间的第一PMOS晶体管和第二和第三NMOS晶体管。 第一PMOS晶体管和第二NMOS晶体管的栅极连接到输入数据。 第三NMOS晶体管的栅极连接到时钟脉冲信号。 第一PMOS晶体管和第二NMOS晶体管之间的第一中间节点的逻辑电平由第一锁存器锁存。 触发器还包括串联连接在电源电压和接地电压之间的第四PMOS晶体管和第五和第六NMOS晶体管。 第四PMOS晶体管和第五NMOS晶体管的栅极连接到第一中间节点。 第六个NMOS晶体管的栅极连接到时钟脉冲信号。 第四PMOS晶体管和第五NMOS晶体管之间的第二中间节点的逻辑电平由第二锁存器锁存。 因此,触发器的中间节点在逻辑电平切换而不是三个或更多时通过两个NMOS晶体管连接到接地电压,从而缩短了器件的切换时间。
    • 8. 发明申请
    • HIGH SPEED FLIP-FLOPS AND COMPLEX GATES USING THE SAME
    • US20080061853A1
    • 2008-03-13
    • US11926664
    • 2007-10-29
    • Min-su Kim
    • Min-su Kim
    • H03K3/356H03K19/0175
    • H03K3/012H03K3/356121H03K3/356191H03K19/20
    • In high-speed flip-flops and complex gates using the same, the flip-flop includes a first PMOS transistor and second and third NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the first PMOS transistor and the second NMOS transistor are connected to input data. A gate of the third NMOS transistor is connected to a clock pulse signal. A logic level of a first intermediate node between the first PMOS transistor and the second NMOS transistor is latched by a first latch. The flip-flop further includes a fourth PMOS transistor and fifth and sixth NMOS transistors, which are serially connected between a power supply voltage and a ground voltage. Gates of the fourth PMOS transistor and the fifth NMOS transistor are connected to the first intermediate node. A gate of the sixth NMOS transistor is connected to the clock pulse signal. A logic level of a second intermediate node between the fourth PMOS transistor and the fifth NMOS transistor is latched by a second latch. Accordingly, intermediate nodes of the flip-flops are connected to ground voltages via two NMOS transistors upon logic level switching, rather than three or more, so that the switching time of the device is shortened.