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1. 发明授权

US08664978B2 Methods and apparatus for time to current conversion 有权
标题翻译：时间到当前转换的方法和装置
公开(公告)号：US08664978B2
公开(公告)日：2014-03-04
申请号：US13221628
申请日：2011-08-30
申请人： Chung-Ting Lu , Chung-Chieh Yang , Chin-Hua Wen , Chih-Chiang Chang
发明人： Chung-Ting Lu , Chung-Chieh Yang , Chin-Hua Wen , Chih-Chiang Chang
IPC分类号： H03D13/00 , H03K3/017
CPC分类号： H03K5/131 , H03K5/135
摘要： A time to current conversion apparatus and methods. An impedance having an input for selectively receiving a time varying periodic signal or a known voltage signal is provided; and a current output is coupled to the impedance. By observing the average current through the impedance for the known voltage signal over a time period, and by observing the average current through the impedance for a time varying periodic signal, the duty cycle of the time varying periodic signal may be determined by evaluating a ratio of a first average current observed at the current output while the time varying periodic signal is coupled to the impedance to a second average current observed at the current output while the known voltage signal is coupled to the impedance. An embodiment time to current converter circuit is disclosed. Method embodiments for determining the duty cycle of a time varying periodic signal are provided.
摘要翻译：一个时间到当前的转换设备和方法。提供具有用于选择性地接收时变周期信号或已知电压信号的输入的阻抗; 并且电流输出耦合到阻抗。通过在一段时间内观察已知电压信号的阻抗的平均电流，并且通过观察时变周期信号的通过阻抗的平均电流，可以通过评估时变周期信号的占空比来确定时变周期信号的占空比在电流输出处观察到的第一平均电流，而当所述已知电压信号耦合到所述阻抗时，所述时变周期信号与所述阻抗耦合到在所述电流输出处观察到的第二平均电流。公开了一种实时的电流转换器电路。提供了用于确定时变周期信号的占空比的方法实施例。

2. 发明申请

US20130049810A1 Methods and Apparatus for Time to Current Conversion 有权
标题翻译：时间到当前转换的方法和装置
公开(公告)号：US20130049810A1
公开(公告)日：2013-02-28
申请号：US13221628
申请日：2011-08-30
申请人： Chung-Ting Lu , Chung-Chieh Yang , Chin-Hua Wen , Chih-Chiang Chang
发明人： Chung-Ting Lu , Chung-Chieh Yang , Chin-Hua Wen , Chih-Chiang Chang
IPC分类号： H03D13/00
CPC分类号： H03K5/131 , H03K5/135
摘要： A time to current conversion apparatus and methods. An impedance having an input for selectively receiving a time varying periodic signal or a known voltage signal is provided; and a current output is coupled to the impedance. By observing the average current through the impedance for the known voltage signal over a time period, and by observing the average current through the impedance for a time varying periodic signal, the duty cycle of the time varying periodic signal may be determined by evaluating a ratio of a first average current observed at the current output while the time varying periodic signal is coupled to the impedance to a second average current observed at the current output while the known voltage signal is coupled to the impedance. An embodiment time to current converter circuit is disclosed. Method embodiments for determining the duty cycle of a time varying periodic signal are provided.
摘要翻译：一个时间到当前的转换设备和方法。提供具有用于选择性地接收时变周期信号或已知电压信号的输入的阻抗; 并且电流输出耦合到阻抗。通过在一段时间内观察已知电压信号的阻抗的平均电流，并且通过观察时变周期信号的通过阻抗的平均电流，可以通过评估时变周期信号的占空比来确定时变周期信号的占空比在电流输出处观察到的第一平均电流，而当所述已知电压信号耦合到所述阻抗时，所述时变周期信号与所述阻抗耦合到在所述电流输出处观察到的第二平均电流。公开了一种实时的电流转换器电路。提供了用于确定时变周期信号的占空比的方法实施例。

3. 发明授权

US08719755B2 Graded dummy insertion 有权
标题翻译：分级虚拟插入
公开(公告)号：US08719755B2
公开(公告)日：2014-05-06
申请号：US13562638
申请日：2012-07-31
申请人： Wen-Shen Chou , Yung-Chow Peng , Chih-Chiang Chang , Chin-Hua Wen
发明人： Wen-Shen Chou , Yung-Chow Peng , Chih-Chiang Chang , Chin-Hua Wen
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.
摘要翻译：除此之外，本文提供了用于分级虚拟插入的一种或多种技术和所得到的阵列。例如，阵列是金属氧化物半导体（MOS）阵列，金属氧化物金属（MOM）阵列或电阻阵列。在一些实施例中，基于与第一区域相关联的第一图案密度与与第二区域相关联的第二图案密度之间的密度梯度来识别第一区域和第二区域。例如，第一图案密度和第二图案密度是门密度和/或多密度。为此，在第一区域和第二区域之间插入虚拟区域，虚拟区域包括基于第一相邻图案密度和第二相邻图案密度的渐变图案密度。以这种方式，提供分级虚拟插入，从而提高阵列的边缘单元性能。

4. 发明申请

US20140040836A1 GRADED DUMMY INSERTION 有权
标题翻译：分级DUMMY插入
公开(公告)号：US20140040836A1
公开(公告)日：2014-02-06
申请号：US13562638
申请日：2012-07-31
申请人： Wen-Shen Chou , Yung-Chow Peng , Chih-Chiang Chang , Chin-Hua Wen
发明人： Wen-Shen Chou , Yung-Chow Peng , Chih-Chiang Chang , Chin-Hua Wen
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： Among other things, one or more techniques for graded dummy insertion and a resulting array are provided herein. For example an array is a metal oxide semiconductor (MOS) array, a metal oxide metal (MOM) array, or a resistor array. In some embodiments, a first region and a second region are identified based on a density gradient between a first pattern density associated with the first region and a second pattern density associated with the second region. For example, the first pattern density and the second pattern density are gate densities and/or poly densities. To this end, a dummy region is inserted between the first region and the second region, the dummy region includes a graded pattern density based on a first adjacent pattern density and a second adjacent pattern density. In this manner, graded dummy insertion is provided, thus enhancing edge cell performance for an array, for example.
摘要翻译：除此之外，本文提供了用于分级虚拟插入的一种或多种技术和所得到的阵列。例如，阵列是金属氧化物半导体（MOS）阵列，金属氧化物金属（MOM）阵列或电阻阵列。在一些实施例中，基于与第一区域相关联的第一图案密度与与第二区域相关联的第二图案密度之间的密度梯度来识别第一区域和第二区域。例如，第一图案密度和第二图案密度是门密度和/或多密度。为此，在第一区域和第二区域之间插入虚拟区域，虚拟区域包括基于第一相邻图案密度和第二相邻图案密度的渐变图案密度。以这种方式，提供分级虚拟插入，从而提高阵列的边缘单元性能。

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