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1. 发明授权

US08471483B2 Multi-channel LED driving system 失效
标题翻译：多通道LED驱动系统
公开(公告)号：US08471483B2
公开(公告)日：2013-06-25
申请号：US13090358
申请日：2011-04-20
申请人： Chung-Shu Lee , Jung-Chang Lu , Fa-Ping Wang , Kun-Yu Hsieh
发明人： Chung-Shu Lee , Jung-Chang Lu , Fa-Ping Wang , Kun-Yu Hsieh
IPC分类号： H05B37/00
CPC分类号： H05B33/0815 , H05B33/0827
摘要： A multi-channel LED driving system includes a power adapter, a rectifying and filtering unit, a plurality of LED strings, and a plurality of linear regulators, a CC/CV controller, an optically coupled isolator and a PWM controller. The CC/CV controller detects the conducting currents flowing though the LED strings and DC voltage source outputting from the rectifying and filtering unit, and provides voltage compensation of the power adaptor. In addition, the linear regulators slightly modulate the current difference between the LED strings to achieve current-sharing control, thus stabilize the illuminating brightness generating by the LED.
摘要翻译：多通道LED驱动系统包括电源适配器，整流滤波单元，多个LED串和多个线性调节器，CC / CV控制器，光耦合隔离器和PWM控制器。 CC / CV控制器检测通过LED串流动的导通电流和从整流滤波器输出的直流电压源，并提供电源适配器的电压补偿。此外，线性稳压器会轻微调制LED串之间的电流差异，以实现电流共享控制，从而稳定LED产生的照明亮度。

2. 发明授权

US08670251B2 Regulating apparatus with soft-start and fast-shutdown function 失效
标题翻译：具有软启动和快速关断功能的调节装置
公开(公告)号：US08670251B2
公开(公告)日：2014-03-11
申请号：US13367926
申请日：2012-02-07
申请人： Jung-Chang Lu , Chi-Shin Chu , Chung-Shu Lee
发明人： Jung-Chang Lu , Chi-Shin Chu , Chung-Shu Lee
IPC分类号： H02M1/36
CPC分类号： H02M1/36
摘要： A regulating apparatus with soft-start and fast-shutdown function is applied to a voltage-supplying apparatus. The regulating apparatus includes a soft-start and fast-shutdown circuit, a regulating circuit, and a ground circuit. When voltages are supplied from the voltage-supplying apparatus to the soft-start and fast-shutdown circuit, the regulating circuit, and the ground circuit, the ground circuit is connected to ground, so that the starting time of the regulating circuit is delayed by the soft-start and fast-shutdown circuit. When voltages are not supplied from the voltage-supplying apparatus to the soft-start and fast-shutdown circuit, the regulating circuit, and the ground circuit, the ground circuit is not connected to ground, so that the regulating circuit is shut down fast by the soft-start and fast-shutdown circuit.
摘要翻译：具有软启动和快速关断功能的调节装置被应用于电压供应装置。调节装置包括软启动和快速关断电路，调节电路和接地电路。当从供电装置向软启动和快速关断电路，调节电路和接地电路提供电压时，接地电路接地，使得调节电路的启动时间延迟软启动和快速关断电路。当电压供给装置未向软启动和快速关断电路，调节电路和接地电路供电时，接地电路未接地，使调节电路快速关闭软启动和快速关断电路。

3. 发明申请

US20050146937A1 Flash memory with trench select gate and fabrication process 有权
公开(公告)号：US20050146937A1
公开(公告)日：2005-07-07
申请号：US11059475
申请日：2005-02-16
申请人： Der-Tsyr Fan , Jung-Chang Lu , Chiou-Feng Chen , Prateep Tuntasood
发明人： Der-Tsyr Fan , Jung-Chang Lu , Chiou-Feng Chen , Prateep Tuntasood
IPC分类号： G11C11/34 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8239 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/76 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0433 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/66825
摘要： Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.

4. 发明授权

US06894339B2 Flash memory with trench select gate and fabrication process 有权
标题翻译：具有沟槽选择栅和制作工艺的闪存
公开(公告)号：US06894339B2
公开(公告)日：2005-05-17
申请号：US10336639
申请日：2003-01-02
申请人： Der-Tsyr Fan , Jung-Chang Lu , Chiou-Feng Chen , Prateep Tuntasood
发明人： Der-Tsyr Fan , Jung-Chang Lu , Chiou-Feng Chen , Prateep Tuntasood
IPC分类号： G11C11/34 , G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8239 , H01L21/8247 , H01L27/105 , H01L27/115 , H01L29/423 , H01L29/76 , H01L29/788
CPC分类号： H01L27/115 , G11C16/0433 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/66825
摘要： Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.
摘要翻译：闪存和制造过程，其中在堆叠的，自对准的浮动和控制栅极之间的沟槽中用选择栅极形成存储器单元，其中由选择栅极选通的掩埋的源极和漏极区域。擦除路径形成在浮动栅极和选择栅极的突出的圆形边缘之间，并且编程路径从选择栅极之间的中间沟道区域和通过栅极氧化物的浮动栅极延伸到浮动栅极的边缘。根据阵列结构，可以在浮动和控制栅极的一侧或两侧设置倾斜的选择栅极，并且在蚀刻衬底和其它材料以形成沟槽时将堆叠的栅极和覆盖它们的电介质用作自对准掩模。

5. 发明授权

US07037787B2 Flash memory with trench select gate and fabrication process 有权
标题翻译：具有沟槽选择栅和制作工艺的闪存
公开(公告)号：US07037787B2
公开(公告)日：2006-05-02
申请号：US11059475
申请日：2005-02-16
申请人： Der-Tsyr Fan , Jung-Chang Lu , Chiou-Feng Chen , Prateep Tuntasood
发明人： Der-Tsyr Fan , Jung-Chang Lu , Chiou-Feng Chen , Prateep Tuntasood
IPC分类号： H01L29/336
CPC分类号： H01L27/115 , G11C16/0433 , H01L21/28273 , H01L27/11521 , H01L29/42328 , H01L29/42336 , H01L29/66825
摘要： Flash memory and process of fabrication in which memory cells are formed with select gates in trenches between stacked, self-aligned floating and control gates, with buried source and drain regions which are gated by the select gates. Erase paths are formed between projecting rounded edges of the floating gates and the select gates, and programming paths extend from the mid-channel regions between the select gates and floating gates through the gate oxide to the edges of the floating gates. Trenched select gates can be provided on one or both sides of the floating and control gates, depending upon array architecture, and the stacked gates and dielectric covering them are used as a self-aligned mask in etching the substrate and other materials to form the trenches.
摘要翻译：闪存和制造过程，其中在堆叠的，自对准的浮动和控制栅极之间的沟槽中用选择栅极形成存储器单元，其中由选择栅极选通的掩埋的源极和漏极区域。擦除路径形成在浮动栅极和选择栅极的突出的圆形边缘之间，并且编程路径从选择栅极之间的中间沟道区域和通过栅极氧化物的浮动栅极延伸到浮动栅极的边缘。根据阵列结构，可以在浮动和控制栅极的一侧或两侧设置倾斜的选择栅极，并且在蚀刻衬底和其它材料以形成沟槽时将堆叠的栅极和覆盖它们的电介质用作自对准掩模。

6. 发明授权

US06885586B2 Self-aligned split-gate NAND flash memory and fabrication process 有权
标题翻译：自对准分闸门NAND闪存和制造工艺
公开(公告)号：US06885586B2
公开(公告)日：2005-04-26
申请号：US10251664
申请日：2002-09-19
申请人： Chiou-Feng Chen , Der-Tsyr Fan , Jung-Chang Lu , Prateep Tuntasood
发明人： Chiou-Feng Chen , Der-Tsyr Fan , Jung-Chang Lu , Prateep Tuntasood
IPC分类号： G11C16/04 , H01L21/8247 , H01L27/115 , G11C7/00
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11524
摘要： Self-aligned split-gate NAND flash memory cell array and method of fabrication in which a series of self-aligned split cells are formed between a bit line diffusion and a common source diffusion. Each cell has control and floating gates which are stacked and self-aligned with each other, and a third gate which is split from but self-aligned with the other two. In some disclosed embodiments, the split gates are utilized as erase gates, and in others they are utilized as select gates. The memory cells are substantially smaller than prior art cells, and the array is biased so that all of the memory cells in it can be erased simultaneously, while programming is bit selectable.
摘要翻译：自对准分离栅极NAND闪存单元阵列及其制造方法，其中在位线扩散与公共源极扩散之间形成一系列自对准分裂单元。每个单元具有彼此堆叠和自对准的控制和浮动栅极，以及与另外两个分离而自对准的第三栅极。在一些公开的实施例中，分裂门用作擦除栅极，而在其它实施例中，它们被用作选择栅极。存储器单元比现有技术的单元小得多，并且阵列被偏置，使得其中的所有存储单元可以被同时擦除，而编程是位可选择的。

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