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    • 2. 发明授权
    • Sectional electric drive vehicle
    • 剖面电动车
    • US08374741B2
    • 2013-02-12
    • US12825542
    • 2010-06-29
    • Chung-Jen HsiehMing-Shiu Ou Yang
    • Chung-Jen HsiehMing-Shiu Ou Yang
    • B60L9/00B60L11/00
    • B62K13/06B62K2204/00
    • A sectional electric drive vehicle includes a first motorcycle having a master electric control unit, a second motorcycle detachably connected to the first motorcycle in tandem by a connection mechanism and the second motorcycle including a slave electric control unit, and a system connector detachably connecting the master electric control unit and the slave electric control unit, to allow signals transmission between the master and slave electric control units. When the first and second motorcycles are combined and connected together via the connection mechanism and the system connector, the slave electric control unit relinquishes control to the master electric control unit, and the master electric control unit controls the cooperative motion of the first and second motorcycles. When the first and second motorcycles are detached, the first and second motorcycles are independently operable.
    • 分段电动车辆包括具有主电控单元的第一摩托车,通过连接机构串联连接到第一摩托车的第二摩托车,以及包括从电控制单元的第二摩托车,以及可拆卸地连接主控制器的系统连接器 电气控制单元和从属电气控制单元,以允许主从电气单元之间的信号传输。 当第一和第二摩托车通过连接机构和系统连接器组合并连接在一起时,从属电气控制单元放弃对主电控单元的控制,主电控单元控制第一和第二摩托车的协同运动 。 当第一和第二摩托车拆卸时,第一和第二摩托车可独立操作。
    • 3. 发明授权
    • System and method for testing hard disk ports
    • 用于测试硬盘端口的系统和方法
    • US08443238B2
    • 2013-05-14
    • US13095876
    • 2011-04-28
    • Ming-Xiang HuMing-Shiu Ou YangJun-Min ChenGe-Xin ZengShuang Peng
    • Ming-Xiang HuMing-Shiu Ou YangJun-Min ChenGe-Xin ZengShuang Peng
    • G06F11/00
    • G06F11/2221
    • A method tests hard disk ports located on a motherboard of a computing device. Each of the hard disk ports connects to a respective serial port of a test fixture. The test fixture includes a group of serial ports, a multiplexer and a storage device. Each of the hard disk ports is selected to be tested during the process of hard disk ports test. A data transmission path is formed by building a connection between the storage device and a channel of the multiplexer corresponding to the hard disk port. Data are written to the storage device and read from the storage device through the data transmission path. The hard disk port is working normal if the written data are identical to the read data. The hard disk port is not working normally if the written data are not identical to the read data.
    • 一种方法来测试位于计算设备主板上的硬盘端口。 每个硬盘端口连接到测试夹具的相应串行端口。 测试夹具包括一组串行端口,多路复用器和存储设备。 在硬盘端口测试过程中,选择每个硬盘端口进行测试。 数据传输路径通过在存储设备和与硬盘端口相对应的多路复用器的通道之间建立连接来形成。 数据被写入存储装置,并通过数据传输路径从存储装置读取。 如果写入的数据与读取的数据相同,则硬盘端口正常工作。 如果写入的数据与读取的数据不同,则硬盘端口不能正常工作。
    • 4. 发明授权
    • System and method for testing the accuracy of real time clocks
    • 用于测试实时时钟精度的系统和方法
    • US07711517B2
    • 2010-05-04
    • US12107784
    • 2008-04-23
    • Ming-Shiu Ou YangWei-Yuan Chen
    • Ming-Shiu Ou YangWei-Yuan Chen
    • G04F1/00
    • G06F1/14G01R31/31727
    • A method for testing the accuracy of real time clocks is disclosed. The method includes the steps of: setting test parameters for testing the accuracy of real time clocks (RTCs), the test parameters comprising a test time length, a test time sampling interval, and an acceptable margin; synchronizing the time of an RTC IC and an RTC to be tested via a UUT; reading a current time of the RTC IC and the RTC via the UUT at each test time sampling interval; calculating a time difference between the current time of the RTC IC and the RTC via the UUT, and measuring whether the absolute value of the time difference is less than the acceptable margin; detecting whether the test time length is over; repeating the test process if the test time length is not over, or outputting test pass information if the test time length is over. A related system is also disclosed.
    • 公开了一种用于测试实时时钟精度的方法。 该方法包括以下步骤:设置用于测试实时时钟(RTC)精度的测试参数,测试参数包括测试时间长度,测试时间采样间隔和可接受余量; 通过UUT同步RTC IC和要测试的RTC的时间; 每个测试时间采样间隔通过UUT读取RTC IC和RTC的当前时间; 通过UUT计算RTC IC和RTC的当前时间之间的时间差,并测量时差的绝对值是否小于可接受余量; 检测测试时间是否结束; 如果测试时间长度未结束,则重复测试过程,如果测试时间长度结束,则输出测试通过信息。 还公开了相关系统。
    • 5. 发明授权
    • System and method for measuring performance of a voltage regulator module attached to a microprocessor
    • 用于测量连接到微处理器的电压调节器模块的性能的系统和方法
    • US07433800B2
    • 2008-10-07
    • US11309030
    • 2006-06-12
    • Ming-Shiu Ou YangWei-Yuan ChenSung-Kuo KuCho-Hao Wang
    • Ming-Shiu Ou YangWei-Yuan ChenSung-Kuo KuCho-Hao Wang
    • G01R31/02
    • G01R19/16552
    • A system for measuring performance of a voltage regulator module (VRM) attached to a microprocessor includes: a voltage transient tester (VTT) fixture (5) for setting different working voltage levels of the VRM; an oscillograph (2) for measuring transient voltage levels of the VRM, and generating a transient voltage waveform according to the transient voltage levels; an voltmeter (3) for measuring steady voltage levels of the VRM under thermal effects generated by the microprocessor; a direct current (DC) electronic load (4) for educing load currents from the VRM; and a measurement control module (10) installed in a computer (1) for generating load current control signals, controlling the DC electronic load to educe the load currents from the VRM according to the load current control signals, and generating a performance report of the VRM by integrating various measurement results.
    • 用于测量附接到微处理器的电压调节器模块(VRM)的性能的系统包括:用于设置VRM的不同工作电压电平的电压瞬变测试器(VTT)固定装置(5); 用于测量VRM的瞬态电压电平的示波器(2),以及根据瞬态电压电平产生瞬态电压波形; 用于在由微处理器产生的热效应下测量VRM的稳定电压电平的电压表(3); 直流(DC)电子负载(4),用于教育来自VRM的负载电流; 以及安装在计算机(1)中的用于产生负载电流控制信号的测量控制模块(10),控制DC电子负载以根据负载电流控制信号从VRM中减少负载电流,并且生成 VRM通过集成各种测量结果。