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1. 发明申请

US20080159459A1 Methods and apparatus to provide clock resynchronization in communication networks 有权
标题翻译：在通信网络中提供时钟重新同步的方法和装置
公开(公告)号：US20080159459A1
公开(公告)日：2008-07-03
申请号：US11653534
申请日：2007-01-16
申请人： Chung San Roger Chan , Richard M. Prentice , Woo Jin Kim
发明人： Chung San Roger Chan , Richard M. Prentice , Woo Jin Kim
IPC分类号： H04L7/00
CPC分类号： H04L7/033
摘要： Methods and apparatus to provide clock resynchronization in communication networks are disclosed. An example method of clock resynchronization disclosed herein comprises determining a vote based on adjacent samples occurring within a single bit interval in a sampled data stream, wherein the vote comprises an early vote when the adjacent samples indicate a sampling phase of a sampling clock is early relative to a center position in the bit interval and wherein the vote comprises a late vote when adjacent samples indicate the sampling phase is late relative to the center position, tracking a running difference between a number of early votes and a number of late votes in a plurality of votes corresponding to a plurality of adjacent samples, and adjusting the sampling phase when the running difference reaches a threshold.
摘要翻译：公开了在通信网络中提供时钟再同步的方法和装置。本文公开的时钟重新同步的示例性方法包括基于在采样数据流中的单个位间隔内发生的相邻采样来确定投票，其中当相邻采样指示采样时钟的采样相位为早期相对时，投票包括早期投票到所述比特间隔中的中心位置，并且其中所述投票包括晚期投票，当相邻样本指示所述采样阶段相对于所述中心位置较晚时，跟踪多个早期投票与多个晚期投票数之间的差异的投票对应于多个相邻样本，并且当运行差达到阈值时调整采样相位。

2. 发明授权

US08000425B2 Methods and apparatus to provide clock resynchronization in communication networks 有权
标题翻译：在通信网络中提供时钟重新同步的方法和装置
公开(公告)号：US08000425B2
公开(公告)日：2011-08-16
申请号：US11653534
申请日：2007-01-16
申请人： Chung San Roger Chan , Richard M Prentice , Woo Jin Kim
发明人： Chung San Roger Chan , Richard M Prentice , Woo Jin Kim
IPC分类号： H04L7/00
CPC分类号： H04L7/033
摘要： Methods and apparatus to provide clock resynchronization in communication networks are disclosed. An example method of clock resynchronization disclosed herein comprises determining a vote based on adjacent samples occurring within a single bit interval in a sampled data stream, wherein the vote comprises an early vote when the adjacent samples indicate a sampling phase of a sampling clock is early relative to a center position in the bit interval and wherein the vote comprises a late vote when adjacent samples indicate the sampling phase is late relative to the center position, tracking a running difference between a number of early votes and a number of late votes in a plurality of votes corresponding to a plurality of adjacent samples, and adjusting the sampling phase when the running difference reaches a threshold.
摘要翻译：公开了在通信网络中提供时钟再同步的方法和装置。本文公开的时钟重新同步的示例性方法包括基于在采样数据流中的单个位间隔内发生的相邻采样来确定投票，其中当相邻采样指示采样时钟的采样相位为早期相对时，投票包括早期投票到所述比特间隔中的中心位置，并且其中所述投票包括晚期投票，当相邻样本指示所述采样阶段相对于所述中心位置较晚时，跟踪多个早期投票与多个晚期投票数之间的差异的投票对应于多个相邻样本，并且当运行差达到阈值时调整采样相位。

3. 发明授权

US09202742B1 Integrated circuit packaging system with pattern-through-mold and method of manufacture thereof 有权
标题翻译：集成电路封装系统及其制造方法
公开(公告)号：US09202742B1
公开(公告)日：2015-12-01
申请号：US14156271
申请日：2014-01-15
申请人： Woo Jin Kim , Sun Jae Kim , Chung Lyul Ahn , Hyeon Yi Kang
发明人： Woo Jin Kim , Sun Jae Kim , Chung Lyul Ahn , Hyeon Yi Kang
IPC分类号： H01L21/768 , H01L23/522 , H01L21/56 , H01L23/31 , H01L21/52 , H01L23/12 , H01L23/16
CPC分类号： H01L23/49827 , H01L21/52 , H01L21/56 , H01L21/563 , H01L23/12 , H01L23/16 , H01L23/3121 , H01L23/3128 , H01L23/3135 , H01L23/3157 , H01L23/49816 , H01L23/49838 , H01L23/5389 , H01L2224/16225 , H01L2225/06548 , H01L2924/15311 , H01L2924/181 , H01L2924/19105 , H01L2924/00012
摘要： An integrated circuit packaging system, and a method of manufacture thereof, including: a substrate; a device attached on a top surface of the substrate; a mold encapsulating the device, the mold having a through via and a recessed pattern characterized by being formed in a single process; and a conductive via in the through via and a conductive pattern in the recessed pattern characterized by being formed in another single process.
摘要翻译：一种集成电路封装系统及其制造方法，包括：基板; 附着在所述基板的顶表面上的装置; 封装所述装置的模具，所述模具具有通孔和凹陷图案，其特征在于以单一工艺形成; 以及通孔中的导电通孔和凹陷图案中的导电图案，其特征在于在另一个单一工艺中形成。

4. 发明授权

US08041408B2 Battery fastening apparatus and portable terminal using the same 有权
标题翻译：电池固定装置和使用其的便携式终端
公开(公告)号：US08041408B2
公开(公告)日：2011-10-18
申请号：US11453044
申请日：2006-06-15
申请人： Woo Jin Kim
发明人： Woo Jin Kim
IPC分类号： H04M1/00
CPC分类号： H04M1/0262 , H01M2/0207 , H01M2/1066
摘要： A battery fastening apparatus and a portable terminal using the same includes a case an exterior and having a battery seating portion formed on a side so as to be exposed to a surface of the case. A battery is seated on the battery seating portion. A locking knob has a latching protrusion protruding into the battery seating portion so that the battery remains fastened to the battery seating portion. The locking knob is partially exposed to an outside of the case and supported by an elastic member so that the latching protrusion engages with the battery. A stopping lever limits movement of the locking knob when the latching protrusion engages the battery. The battery fastening apparatus prevents the battery from unintentionally detaching from the body of the terminal during operation.
摘要翻译：电池紧固装置和使用该电池固定装置的便携式终端包括外壳，并且具有形成在侧面上以便暴露于外壳表面的电池座部分的外壳。电池座位在电池座上。锁定旋钮具有突出到电池座部分中的闩锁突起，使得电池保持固定到电池座部分。锁定旋钮部分地暴露于壳体的外部并由弹性构件支撑，使得闩锁突起与电池接合。当闩锁突起接合电池时，止动杆限制锁定旋钮的移动。电池固定装置防止电池在操作期间被无意地从终端的主体上分离。

5. 发明授权

US07588996B2 Oxide pattern forming method and patterning method of semiconductor device 失效
标题翻译：半导体器件的氧化物图案形成方法和图案化方法
公开(公告)号：US07588996B2
公开(公告)日：2009-09-15
申请号：US11770983
申请日：2007-06-29
申请人： Hyo Geun Yoon , Woo Jin Kim , Dong Joo Kim , Ji Yong Park , Yong Soo Jung , Geun Min Choi , Young Wok Song , Sang Hyun Lee
发明人： Hyo Geun Yoon , Woo Jin Kim , Dong Joo Kim , Ji Yong Park , Yong Soo Jung , Geun Min Choi , Young Wok Song , Sang Hyun Lee
IPC分类号： H01L21/76
CPC分类号： H01L21/3086 , H01L21/3081 , H01L21/31111 , H01L21/31155
摘要： An oxide pattern forming method comprises forming an oxide layer on a semiconductor substrate, implanting boron ions of not less than 1.0×1016 atoms/cm2 onto the oxide layer in a given region, and wet-etching the oxide layer in the remaining region where the boron ions are not implanted.
摘要翻译：氧化物图案形成方法包括在半导体衬底上形成氧化物层，在给定区域中的氧化物层上注入不少于1.0×10 16原子/ cm 2的硼离子，并在剩余的区域中湿法蚀刻氧化物层，其中硼离子不被植入。

6. 发明申请

US20090122461A1 CAPACITOR FOR A SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 失效
标题翻译：用于半导体器件的电容器及其制造方法
公开(公告)号：US20090122461A1
公开(公告)日：2009-05-14
申请号：US12358175
申请日：2009-01-22
申请人： Pyeong Won OH , Woo Jin Kim , Hoon Jung Oh , Hyo Gun Yoon , Hyo Seob Yoon , Baik II Choi
发明人： Pyeong Won OH , Woo Jin Kim , Hoon Jung Oh , Hyo Gun Yoon , Hyo Seob Yoon , Baik II Choi
IPC分类号： H01G4/06
CPC分类号： H01L28/56 , H01L21/02178 , H01L21/02192 , H01L21/022 , H01L21/02274 , H01L21/0234 , H01L21/31604 , H01L21/31616 , H01L27/10817 , H01L27/10852 , H01L28/91
摘要： Disclosed is a capacitor for a semiconductor device, comprising: a lower electrode formed over a predetermined lower structure on a semiconductor substrate; an aluminum oxynitride film formed over the lower electrode and having a low leakage current characteristic; a yttrium oxynitride film formed over the aluminum oxynitride film and having a higher dielectric constant than the aluminum oxynitride film; and an upper electrode formed over the yttrium oxynitride film, and a manufacturing method thereof.
摘要翻译：公开了一种用于半导体器件的电容器，包括：在半导体衬底上形成在预定下部结构上的下电极; 形成在下电极上并具有低漏电流特性的氧氮化铝膜; 形成在氮氧化铝膜上并具有比氮氧化铝膜更高的介电常数的氧化钇膜; 和形成在氧氮化钇膜上的上电极及其制造方法。

7. 发明授权

US07410909B2 Method of removing ion implanted photoresist 失效
标题翻译：去除离子注入光刻胶的方法
公开(公告)号：US07410909B2
公开(公告)日：2008-08-12
申请号：US11646700
申请日：2006-12-28
申请人： Ji Hye Han , Ok Min Moon , Woo Jin Kim , Hyo Seob Yoon , Ji Yong Park , Kee Joon Oh
发明人： Ji Hye Han , Ok Min Moon , Woo Jin Kim , Hyo Seob Yoon , Ji Yong Park , Kee Joon Oh
IPC分类号： H01L21/461 , H01L21/302
CPC分类号： H01L21/31133 , G03F7/423 , G03F7/428
摘要： A method of removing an ion implanted photoresist comprises performing first cleaning a semiconductor substrate having the ion implanted photoresist using hot deionized water to which a megasonic process is applied, first rinsing the semiconductor substrate using cold deionized water, drying the semiconductor substrate, removing the ion implanted photoresist, and second cleaning the semiconductor wafer using an SPM solution.
摘要翻译：去除离子注入光致抗蚀剂的方法包括使用施加了兆声波处理的热去离子水对第一次清洗具有离子注入光致抗蚀剂的半导体衬底，首先使用冷去离子水冲洗半导体衬底，干燥半导体衬底，去除离子并且使用SPM解决方案来第二次清洁半导体晶片。

8. 发明申请

US20080003769A1 Method for fabricating semiconductor device having trench isolation layer 有权
标题翻译：制造具有沟槽隔离层的半导体器件的方法
公开(公告)号：US20080003769A1
公开(公告)日：2008-01-03
申请号：US11647929
申请日：2006-12-29
申请人： Hyo Seob Yoon , Woo Jin Kim , Ok Min Moon , Ji Yong Park
发明人： Hyo Seob Yoon , Woo Jin Kim , Ok Min Moon , Ji Yong Park
IPC分类号： H01L21/76
CPC分类号： H01L21/76224 , H01L27/105 , H01L27/1052
摘要： A method for fabricating a device isolation structure of a semiconductor device includes the steps of forming a pad oxide layer and a pad nitride layer over a semiconductor substrate including a cell region and a dummy region, etching a portion of the pad nitride layer, the pad oxide layer and the semiconductor substrate to form a trench, forming a sidewall oxide layer over the sidewalls of the trench; removing the sidewall oxide layer in the dummy region, forming a silicon nitride layer over the sidewalls of the sidewall oxide layer both in the cell region and in the dummy region, filling the trench with an insulating layer, polishing the insulating layer to expose the pad nitride layer, and removing the pad nitride layer.
摘要翻译：一种制造半导体器件的器件隔离结构的方法包括以下步骤：在包括单元区域和虚拟区域的半导体衬底上形成衬垫氧化物层和衬垫氮化物层，蚀刻衬垫氮化物层的一部分，衬垫氧化物层和半导体衬底以形成沟槽，在沟槽的侧壁上形成侧壁氧化物层; 去除虚设区域中的侧壁氧化物层，在单元区域和虚拟区域中的侧壁氧化物层的侧壁上形成氮化硅层，用绝缘层填充沟槽，抛光绝缘层以露出衬垫氮化物层，以及去除衬垫氮化物层。

9. 发明申请

US20080001625A1 BIDIRECTIONAL DATA REPEATER SWITCH 有权
公开(公告)号：US20080001625A1
公开(公告)日：2008-01-03
申请号：US11745539
申请日：2007-05-08
申请人： Julie A. Hwang , Woo Jin Kim , Alan S. Bass , Mark W. Morgan
发明人： Julie A. Hwang , Woo Jin Kim , Alan S. Bass , Mark W. Morgan
IPC分类号： H03K19/003
CPC分类号： H03K19/0185
摘要： A bidirectional repeater and data multiplexer for serial data comprises a plurality of comparators 302, 304, 306, 308 coupled to the respective input/output (I/O) terminals of a plurality of serial data transceiver devices A1, A2, A3, A4 such as used in I2C communication. Also coupled to these I/O terminals is a plurality of active pulldowns 316, 318, 320, 322. The outputs of the comparators are coupled to N:1 Select 310 logic wherein the desired data input is selected responsive to select lines S1, S2, S3, S4. The output of the N:1 select logic is coupled to a bidirectional control circuit 210, which couples the selected data to the control terminal of an active pulldown 206 having its source coupled to a pulldown voltage Vp low enough to represent a logic “low” level but non-zero, and a drain connected to the I/O terminal of a device B. Also connected to the I/O terminal of device B is an inverting comparator having a threshold voltage Vt somewhat below the pulldown voltage Vp described above, such that the comparator ignores the low level Vp of the active pulldown, but responds to the less than Vp data zero level from device B. This prevents data lockup where data from An would flow back to the same device An. The data output of comparator 208 is thus a repeated version of data present on the I/O terminal of device B, and is coupled through 1:N Select 312 logic, responsive to the same select lines S1 . . . described above, to one of the plurality of active pulldowns 316, 318, 320, 322. Data from device An, one of the plurality of devices A1 . . . A4, is thus repeated and selectively routed to device B. Similarly, data from device B is selectively routed to the active pulldown coupled to the same device An. Pulldown voltages Vp and threshold voltages Vt may be varied to optimize coupling with device B, as long as the pulldown voltage Vp remains above the threshold voltage Vt; the pulldown and threshold voltages may be selected from a plurality of such pulldown and threshold voltages, in order to optimize noise margins when coupling to devices having different Vil and Vol specifications.

10. 发明申请

US20080132073A1 Oxide Pattern Forming Method and Patterning Method of Semiconductor Device 失效
标题翻译：半导体器件的氧化物图案形成方法和图案化方法
公开(公告)号：US20080132073A1
公开(公告)日：2008-06-05
申请号：US11770983
申请日：2007-06-29
申请人： Hyo Geun Yoon , Woo Jin Kim , Dong Joo Kim , Ji Yong Park , Yong Soo Jung , Geun Min Choi , Young Wok Song , Sang Hyun Lee
发明人： Hyo Geun Yoon , Woo Jin Kim , Dong Joo Kim , Ji Yong Park , Yong Soo Jung , Geun Min Choi , Young Wok Song , Sang Hyun Lee
IPC分类号： H01L21/311
CPC分类号： H01L21/3086 , H01L21/3081 , H01L21/31111 , H01L21/31155
摘要： An oxide pattern forming method comprises forming an oxide layer on a semiconductor substrate, implanting boron ions of not less than 1.0×1016 atoms/cm2 onto the oxide layer in a given region, and wet-etching the oxide layer in the remaining region where the boron ions are not implanted.
摘要翻译：氧化物图案形成方法包括在半导体衬底上形成氧化物层，在给定的氧化物层中将不少于1.0×10 16原子/ cm 2的硼离子注入到氧化物层上区域，并且在没有植入硼离子的剩余区域中湿法蚀刻氧化物层。

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