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1. 发明授权

US5781529A Systems and methods for routing ATM switched virtual circuit calls 失效
标题翻译：用于路由ATM交换虚拟电路呼叫的系统和方法
公开(公告)号：US5781529A
公开(公告)日：1998-07-14
申请号：US624812
申请日：1996-03-27
申请人： Chung C. Liang , Javier R. Rojas , Kuldip S. Bains
发明人： Chung C. Liang , Javier R. Rojas , Kuldip S. Bains
IPC分类号： H04L12/56 , H04Q11/04
CPC分类号： H04L49/3081 , H04L49/253 , H04L49/255 , H04Q11/0478 , H04L2012/563 , H04L49/30
摘要： The invention routes SVC ATM call setups by utilizing one of a plurality of designated transit lists (DTLs) stored at an originating node. The DTLs describe all routes in the network from the originating node to endpoint destinations. When a call setup message is received at the originating node, it inserts a desired DTL as an information element (IE) of the setup message. Each DTL is formatted as a concatenation of elements with each element including the node ID and output ports of each successive node in the route. Preferably, each element of the DTL includes flags such as a "process" flag which indicates whether an element of the DTL has been processed by a node, a "link up" flag which indicates that an alternative route is available between two nodes should the preferred route be down, a "bandwidth" flag which allows the alternate link to be used if the preferred link is busy, and a "last node" flag which is used in the last element of the concatenated DTL. If the "last node" flag is not set, the destination node internally generates a route ID as the last element based on the destination address specified in an IE for the call. As the DTL IE is passed from node to node along the connection path, the receiving node inserts the input port at which it received the call setup message as well as a VPI/VCI into its element of the DTL. At its destination, the DTL is attached to a CONNECT request message which is returned to the source node.
摘要翻译：本发明通过利用存储在始发节点的多个指定转接列表（DTL）中的一个来路由SVC ATM呼叫建立。 DTL描述了从始发节点到端点目的地的网络中的所有路由。当在始发节点接收到呼叫建立消息时，它插入期望的DTL作为建立消息的信息元素（IE）。每个DTL被格式化为每个元素的级联，每个元素包括路由中每个连续节点的节点ID和输出端口。优选地，DTL的每个元素包括诸如表示DTL的元素是否已被节点处理的“进程”标志的标志，指示替代路由在两个节点之间可用的“链路向上”标志，如果优先路由被关闭，如果优选链路忙时允许使用替代链路的“带宽”标志，以及在级联DTL的最后一个元素中使用的“最后一个节点”标志。如果未设置“最后节点”标志，则目的地节点根据用于该呼叫的IE中指定的目的地地址内部生成路由ID作为最后一个元素。当DTL IE沿着连接路径从节点传递到节点时，接收节点将其接收呼叫建立消息的输入端口以及VPI / VCI插入到其DTL的元素中。在其目的地，DTL附加到返回到源节点的CONNECT请求消息。

2. 发明授权

US4888770A Algorithm for selecting channels for multiplexer frame 失效
标题翻译：选择多路复用帧通道的算法
公开(公告)号：US4888770A
公开(公告)日：1989-12-19
申请号：US259856
申请日：1988-10-19
申请人： Kuldip S. Bains
发明人： Kuldip S. Bains
IPC分类号： H04J3/16
CPC分类号： H04J3/1682
摘要： An algorithm for ordering selects for a plurality of channels to be multiplexed into a frame is provided. A channel ready counter and a channel select position counter for each of the channels to be multiplexed are initialized. The first and succeeding channel selects are chosen based primarily on the respective values of the channel ready counters such that a channel having a ready counter of relative higher value is always selected before a channel having a ready counter of relative lower value. Where channel ready counter integer values of more than one channel are equal, the select is chosen on the secondary basis of channel rate, with the highest rate channel of the highest ready count contributing first. After a select is made, the ready counter of the selected channel is determined, and the position counters of the channels are decremented by a value corresponding to the number of selects for that channel in the frame. If the position counter of a channel reach zero or goes negative as a result of the decrementing, the position counter of that channel is increased by the total number of selects in the frame, and the ready counter for that channel is incremented by one. After such updating, another selection for the frame may be made based on the ready counter values of the channels. The provided algorithm guarantees that no channel will ever have an excursion of more than one bit available for placement in the frame.
摘要翻译：提供了一种用于排序的多路复用通道的选择算法。初始化要复用的每个信道的信道准备计数器和信道选择位置计数器。主要基于通道就绪计数器的相应值选择第一和后续通道选择，使得在具有相对较低值的准备计数器的通道之前总是选择具有相对较高值的准备计数器的通道。在多于一个通道的通道就绪计数器整数值相等的情况下，在通道速率的次要基础上选择选择，最高准备计数的最高速率通道首先起作用。在进行选择之后，确定所选频道的就绪计数器，并且将通道的位置计数器减少与帧中该通道的选择次数对应的值。如果通道的位置计数器由于递减而达到零或变为负值，则该通道的位置计数器将增加帧中的选择总数，并将该通道的就绪计数器增加1。在这种更新之后，可以基于通道的准备好的计数器值来进行该帧的另一选择。所提供的算法保证没有通道将不会有超过一位可用于放置在帧中的偏移。

3. 发明授权

US4930125A Multiplexer frame synchronization technique 失效
标题翻译：多路复用器帧同步技术
公开(公告)号：US4930125A
公开(公告)日：1990-05-29
申请号：US304015
申请日：1989-01-30
申请人： Kuldip S. Bains
发明人： Kuldip S. Bains
IPC分类号： H04J3/06
CPC分类号： H04J3/0602
摘要： Methods for quickly determining loss of synchronization and for quickly reestablishing synchronization of a sub-aggregate frame having primary and secondary frames and contained within an independently synchronized aggregate are provided. In determining loss of synchronization, synch bits are located in the secondary frame such that when the composite subaggregate frame is synchronized the synch bits are chosen to be inserted into the same predetermined position in the aggregate. The synch bits are provided with values such that a collection of synch bits of a composite frame provides an internally non-repeating pattern. By comparing bit values received in the predetermined location of the aggregate at the synch bit rate with the non-repeating pattern, a determination is made as to whether synchronization has been lost. To reestablish synchronization, during data receipt, the bits located in the predetermined synch bit location in the aggregate frame are sequentially inserted into a number of buffers, the number being equal to the frame rate of the subaggregate divided by the synch rate of the synch bits. Then, upon loss of synchronization, a local pointer value is stored upon receipt of a synch bit candidate, the bit patterns in the buffers are scanned to find the buffer containing the internally non-repeating synch pattern, and a pointer correction indication is determined by comparing the local pointer value to a system pointer value dictated by the buffer found to contain the synch bits, and the phase of the internally non-repeating synch pattern in that buffer.

4. 发明授权

US4881224A Framing algorithm for bit interleaved time division multiplexer 失效
标题翻译：位交错时分复用器的成帧算法
公开(公告)号：US4881224A
公开(公告)日：1989-11-14
申请号：US259803
申请日：1988-10-19
申请人： Kuldip S. Bains
发明人： Kuldip S. Bains
IPC分类号： H04J3/16
CPC分类号： H04J3/1629
摘要： Methods are provided for multiplexing a plurality of channels on to a sub-aggregate of an aggregate line so as to substantially minimize total frame length. In a preferred method, channel data rates are expressed as a sum of a plurality of predetermined subchannel data rates, and the number of times each predetermined subchannel data rate is used to express a channel data rate of a channel to be multiplexed is accumulated. Given a predetermined primary frame rate (P) such as 8Khz for a DACs compatible multiplexer, and a tertiary frame rate (T) chosen as the greatest common denominator of the subchannel data rates, an optimal secondary frame rate (S) may be found by minimizing for a plurality of different secondary frame rates the sum of (P/S) F1 plus (S/T)F2, where F1 represents the number of calls of the primary frame to the secondary frame, and F2 represents the number of calls of the secondary frame to the tertiary frame. Where different primary frame rates may be used, the sum of (A/P) plus (P/S)F1 plus (S/T)F2 is minimized to find primary and secondary frame rates which will permit an optimally small total frame length, given the sub-aggregate rate A.

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