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1. 发明授权

US07301604B2 Method to predict and identify defocus wafers 有权
标题翻译：预测和识别散焦晶圆的方法
公开(公告)号：US07301604B2
公开(公告)日：2007-11-27
申请号：US10786495
申请日：2004-02-25
申请人： Chun-Hung Lin , Louie Liu , Li-Kong Turn , Chi-Hung Liao , Ham-Ming Hsieh , Yi-Chang Sung , Hsin-Chun Chiang
发明人： Chun-Hung Lin , Louie Liu , Li-Kong Turn , Chi-Hung Liao , Ham-Ming Hsieh , Yi-Chang Sung , Hsin-Chun Chiang
IPC分类号： G01B11/00 , G03B27/52
CPC分类号： G03F9/7026 , G01N2021/8416 , G03F7/70533
摘要： A method and system for identifying a defocus wafer by mapping a topography of each wafer in a first wafer batch using a level sensor apparatus (100); calculating a focus spot deviation (402) from the data, the focus spot deviation (402) corresponding to a height by which a focus spot of a photo exposure module would be defocused by the topography; converting the focus spot deviation (402) to a corresponding wafer stage set point to which the photo exposure module is set, to focus the focus spot on each wafer in the wafer batch; and identifying a defocus wafer in the wafer batch, as a wafer having a topography that would defocus the focus spot, even when the photo exposure module is set to the wafer stage set point.
摘要翻译：一种用于通过使用液位传感器装置（100）在第一晶片批次中映射每个晶片的形貌来识别散焦晶片的方法和系统; 从所述数据计算焦点偏差（402），所述焦点偏差（402）对应于所述照相曝光模块的焦点将由所述形貌散焦的高度; 将聚焦点偏差（402）转换为设置有曝光模块的对应的晶片台设定点，以将聚焦点聚焦在晶片批次中的每个晶片上; 并且即使当将曝光模块设置到晶片台设定点时，将晶片批中的散焦晶片识别为具有将焦点聚焦的形貌的晶片。

2. 发明申请

US20050185170A1 Method to predict and identify defocus wafers 有权
标题翻译：预测和识别散焦晶圆的方法
公开(公告)号：US20050185170A1
公开(公告)日：2005-08-25
申请号：US10786495
申请日：2004-02-25
申请人： Chun-Hung Lin , Louie Liu , Li-Kong Turn , Chi-Hung Liao , Ham-Ming Hsieh , Yi-Chang Sung , Hsin-Chun Chiang
发明人： Chun-Hung Lin , Louie Liu , Li-Kong Turn , Chi-Hung Liao , Ham-Ming Hsieh , Yi-Chang Sung , Hsin-Chun Chiang
IPC分类号： G01B9/00 , G01N21/88 , G03F7/20 , G03F9/00 , H01L21/00
CPC分类号： G03F9/7026 , G01N2021/8416 , G03F7/70533
摘要： A method and system for identifying a defocus wafer by mapping a topography of each wafer in a first wafer batch using a level sensor apparatus (100); calculating a focus spot deviation (402) from the data, the focus spot deviation (402) corresponding to a height by which a focus spot of a photo exposure module would be defocused by the topography; converting the focus spot deviation (402) to a corresponding wafer stage set point to which the photo exposure module is set, to focus the focus spot on each wafer in the wafer batch; and identifying a defocus wafer in the wafer batch, as a wafer having a topography that would defocus the focus spot, even when the photo exposure module is set to the wafer stage set point.
摘要翻译：一种用于通过使用液位传感器装置（100）在第一晶片批次中映射每个晶片的形貌来识别散焦晶片的方法和系统; 从所述数据计算焦点偏差（402），所述焦点偏差（402）对应于所述照相曝光模块的焦点将由所述形貌散焦的高度; 将聚焦点偏差（402）转换为设置有曝光模块的对应的晶片台设定点，以将聚焦点聚焦在晶片批次中的每个晶片上; 并且即使当将曝光模块设置到晶片台设定点时，将晶片批中的散焦晶片识别为具有将焦点聚焦的形貌的晶片。

3. 发明授权

US08429569B2 Method and system for feed-forward advanced process control 有权
标题翻译：前馈先进过程控制方法与系统
公开(公告)号：US08429569B2
公开(公告)日：2013-04-23
申请号：US13086935
申请日：2011-04-14
申请人： Chih-Jen Yu , Chun-Hung Lin , Juin-Hung Lin , Hsueh-Yi Chung , Li-Kong Turn , Keh-Wen Chang
发明人： Chih-Jen Yu , Chun-Hung Lin , Juin-Hung Lin , Hsueh-Yi Chung , Li-Kong Turn , Keh-Wen Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G03F7/705 , G03F7/70558 , G03F7/70625
摘要： A method including providing a present wafer to be processed by a photolithography tool, selecting a processed wafer having a past chip design from a plurality of processed wafers, the processed wafer being previously processed by the photolithography tool, selecting a plurality of critical dimension (CD) data points extracted from a plurality of fields on the processed wafer, modeling the plurality of CD data points with a function relating CD to position on the processed wafer, creating a field layout on the present wafer for a new chip design, creating an initial exposure dose map for the new chip design using the function and the field layout, and controlling the exposure of the photolithography tool according to the initial exposure dose map to form the new chip design on the present wafer.
摘要翻译：一种方法，包括提供由光刻工具处理的当前晶片，从多个处理的晶片中选择具有过去晶片设计的经处理的晶片，处理的晶片由光刻工具预先处理，选择多个关键尺寸（CD ）数据点，其处理晶片上的多个场中提取的数据点，以与CD相关的功能对处理的晶片上的位置对多个CD数据点进行建模，在当前晶片上创建用于新芯片设计的场布局，使用功能和现场布局的新芯片设计的曝光剂量图，并根据初始曝光剂量图控制光刻工具的曝光，以在当前晶片上形成新的芯片设计。

4. 发明申请

US20120264063A1 METHOD AND SYSTEM FOR FEED-FORWARD ADVANCED PROCESS CONTROL 有权
标题翻译：前进先进过程控制方法与系统
公开(公告)号：US20120264063A1
公开(公告)日：2012-10-18
申请号：US13086935
申请日：2011-04-14
申请人： Chih-Jen Yu , Chun-Hung Lin , Juin-Hung Lin , Hsueh-Yi Chung , Li-Kong Turn , Keh-Wen Chang
发明人： Chih-Jen Yu , Chun-Hung Lin , Juin-Hung Lin , Hsueh-Yi Chung , Li-Kong Turn , Keh-Wen Chang
IPC分类号： G03F7/20 , G06F17/50
CPC分类号： G06F17/50 , G03F7/705 , G03F7/70558 , G03F7/70625
摘要： A method including providing a present wafer to be processed by a photolithography tool, selecting a processed wafer having a past chip design from a plurality of processed wafers, the processed wafer being previously processed by the photolithography tool, selecting a plurality of critical dimension (CD) data points extracted from a plurality of fields on the processed wafer, modeling the plurality of CD data points with a function relating CD to position on the processed wafer, creating a field layout on the present wafer for a new chip design, creating an initial exposure dose map for the new chip design using the function and the field layout, and controlling the exposure of the photolithography tool according to the initial exposure dose map to form the new chip design on the present wafer.
摘要翻译：一种方法，包括提供将由光刻工具处理的当前晶片，从多个经处理的晶片中选择具有过去芯片设计的处理晶片，处理的晶片由光刻工具预先处理，选择多个临界尺寸（CD ）数据点，其处理晶片上的多个场中提取的数据点，以与CD相关的功能对处理的晶片上的位置对多个CD数据点进行建模，在当前晶片上创建用于新芯片设计的场布局，使用功能和现场布局的新芯片设计的曝光剂量图，并根据初始曝光剂量图控制光刻工具的曝光，以在当前晶片上形成新的芯片设计。

5. 发明授权

US08927314B2 Method of manufacturing solar cell with two exposed surfaces of arc layer disposed at different levels 有权
标题翻译：制造太阳能电池的方法，其具有设置在不同水平的弧形层的两个暴露表面
公开(公告)号：US08927314B2
公开(公告)日：2015-01-06
申请号：US13549814
申请日：2012-07-16
申请人： Sheng Yung Liu , Chin-Tien Yang , Chun-Hung Lin
发明人： Sheng Yung Liu , Chin-Tien Yang , Chun-Hung Lin
IPC分类号： H01L21/00 , H01L31/0224 , H01L31/0216
CPC分类号： H01L31/022433 , H01L31/02168 , Y02E10/50 , Y02E10/52
摘要： A method of manufacturing a solar cell includes the steps of: providing a substrate having a front side, a back side and a doped region; forming a conductor layer on the front side; firing the conductor layer at a temperature such that the conductor layer is formed with a first portion embedded into the doped region and a second portion other than the first portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the conductor layer so that the second portion of the conductor layer is disposed in the ARC layer; and removing the ARC layer on the conductor layer so that the conductor layer has an exposed surface exposed out of the ARC layer, wherein the exposed surface of the conductor layer is substantially flush with a first exposed surface of the ARC layer.
摘要翻译：一种制造太阳能电池的方法包括以下步骤：提供具有正面，背面和掺杂区域的基板; 在前侧形成导体层; 在使得导体层形成有嵌入掺杂区域的第一部分和除了第一部分之外的第二部分的温度下烧制导体层; 在前侧和第二部分形成防反射涂层（ARC）层，其中ARC层覆盖导体层，使得导体层的第二部分设置在ARC层中; 以及去除所述导体层上的所述ARC层，使得所述导体层具有暴露在所述ARC层外部的暴露表面，其中所述导体层的所述暴露表面基本上与所述ARC层的第一暴露表面齐平。

6. 发明授权

US08728851B2 Method of manufacturing solar cell with upper and lower conductor layers stacked together 有权
标题翻译：具有层叠在一起的上下导体层的太阳能电池的制造方法
公开(公告)号：US08728851B2
公开(公告)日：2014-05-20
申请号：US13549877
申请日：2012-07-16
申请人： Sheng Yung Liu , Chin-Tien Yang , Chun-Hung Lin
发明人： Sheng Yung Liu , Chin-Tien Yang , Chun-Hung Lin
IPC分类号： H01L31/18
CPC分类号： H01L31/022433 , H01L31/02168 , Y02E10/50 , Y02E10/52
摘要： A method of manufacturing a solar cell comprises the steps of: forming a lower conductor layer on a front side of a substrate; firing the lower conductor layer at a first temperature to form a first portion embedded into a doped region of the substrate and a second portion; forming an anti-reflection coating (ARC) layer on the front side and the second portion, wherein the ARC layer covers the lower conductor layer such that the second portion is disposed in the ARC layer; forming an upper conductor layer, corresponding to the lower conductor layer and electrically connected to the lower conductor layer, on the ARC layer; and firing the upper conductor layer at a second temperature to form a first portion embedded into the ARC layer and a second portion, which is exposed out of the ARC layer.
摘要翻译：一种制造太阳能电池的方法包括以下步骤：在基板的正面形成下导体层; 在第一温度下焙烧下导体层以形成嵌入衬底的掺杂区域中的第一部分和第二部分; 在前侧和第二部分形成防反射涂层（ARC）层，其中ARC层覆盖下导体层，使得第二部分设置在ARC层中; 在ARC层上形成对应于下导体层并电连接到下导体层的上导体层; 以及在第二温度下烧制所述上导体层以形成嵌入到所述ARC层中的第一部分和暴露在所述ARC层外的第二部分。

7. 发明授权

US08603723B2 Image transfer process 有权
标题翻译：图像传输过程
公开(公告)号：US08603723B2
公开(公告)日：2013-12-10
申请号：US13014285
申请日：2011-01-26
申请人： Hsi-Wen Chang , Wei-Jen Lai , Pi-Ju Chiang , Chun-Hung Lin , Jung Ya Hsieh
发明人： Hsi-Wen Chang , Wei-Jen Lai , Pi-Ju Chiang , Chun-Hung Lin , Jung Ya Hsieh
IPC分类号： G03C5/16 , G03F1/00 , G02F1/03
CPC分类号： G03C11/12 , D06P1/0012 , D06P5/2005
摘要： The present invention relates to an image transfer process. The process includes the steps of: a) providing an image carrying device including at least one photoluminescent surface; b) displaying a luminous image on a display surface of a light-emitting medium; and c) positioning the display surface of the light-emitting medium that is displaying the luminous image at a distance from the at least one photoluminescent surface of the image carrying device shorter than a predetermined effective distance, for a predetermined period of time.
摘要翻译：本发明涉及图像转印处理。该方法包括以下步骤：a）提供包括至少一个光致发光表面的图像承载装置; b）在发光介质的显示表面上显示发光图像; 以及c）将显示所述发光图像的所述发光介质的显示表面定位在比所述图像承载装置的所述至少一个光致发光表面短一预定有效距离的预定时间段。

8. 发明申请

US20130206369A1 HEAT DISSIPATING DEVICE 审中-公开
标题翻译：热灭火装置
公开(公告)号：US20130206369A1
公开(公告)日：2013-08-15
申请号：US13371480
申请日：2012-02-13
申请人： Wei-I Lin , Chien-Chih Yeh , Wen-Shiang Chen , Chun-Hung Lin
发明人： Wei-I Lin , Chien-Chih Yeh , Wen-Shiang Chen , Chun-Hung Lin
IPC分类号： F28D15/04
CPC分类号： F28D15/043
摘要： A heat dissipating device includes a chamber body, a heat sink, a pipe, a first capillary structure and N vapor channels. The chamber body has an evaporation chamber and a compensation chamber, wherein the evaporation chamber has a vapor outlet and the compensation chamber has a liquid inlet. The heat sink is disposed on an outer wall of a first side of the chamber body and at least covers the compensation chamber. The pipe is installed within the heat sink, wherein a first end of the pipe is connected to the vapor outlet and a second end of the pipe is connected to the liquid inlet. The first capillary structure is formed in the evaporation chamber. The N vapor channels are formed in the first capillary structure. The N vapor channels and the compensation chamber are isolated by the first capillary structure.
摘要翻译：散热装置包括室主体，散热器，管，第一毛细管结构和N个蒸气通道。腔体具有蒸发室和补偿室，其中蒸发室具有蒸汽出口，并且补偿室具有液体入口。散热器设置在室主体的第一侧的外壁上，并且至少覆盖补偿室。管道安装在散热器内，其中管道的第一端连接到蒸汽出口，并且管道的第二端连接到液体入口。第一毛细结构形成在蒸发室中。 N蒸汽通道形成在第一毛细管结构中。 N蒸气通道和补偿室由第一毛细管结构隔离。

9. 发明申请

US20130187277A1 CRACK STOPPER ON UNDER-BUMP METALLIZATION LAYER 有权
标题翻译：在下层金属化层的破裂停止
公开(公告)号：US20130187277A1
公开(公告)日：2013-07-25
申请号：US13443556
申请日：2012-04-10
申请人： Yu-Feng Chen , Chun-Hung Lin , Han-Ping Pu , Chih-Hang Tung , Kai-Chiang Wu , Ming-Che Ho
发明人： Yu-Feng Chen , Chun-Hung Lin , Han-Ping Pu , Chih-Hang Tung , Kai-Chiang Wu , Ming-Che Ho
IPC分类号： H01L23/48
CPC分类号： H01L24/13 , H01L23/488 , H01L24/02 , H01L24/05 , H01L24/10 , H01L24/11 , H01L24/16 , H01L2224/0401 , H01L2224/05027 , H01L2224/05111 , H01L2224/05144 , H01L2224/05147 , H01L2224/05155 , H01L2224/05166 , H01L2224/05181 , H01L2224/05186 , H01L2224/05551 , H01L2224/05555 , H01L2224/05572 , H01L2224/05611 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05666 , H01L2224/05681 , H01L2224/05686 , H01L2224/10125 , H01L2224/1146 , H01L2224/1147 , H01L2224/11849 , H01L2224/13012 , H01L2224/13076 , H01L2224/13111 , H01L2224/13113 , H01L2224/13116 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/16237 , H01L2224/16238 , H01L2224/81191 , H01L2924/00014 , H01L2924/01029 , H01L2924/12042 , H01L2924/00012 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/01047 , H01L2224/05552 , H01L2924/00
摘要： A semiconductor die includes a crack stopper on an under-bump metallization (UBM) layer. The crack stopper is in the shape of hollow cylinder with at least two openings.
摘要翻译：半导体管芯包括在凸块下金属化（UBM）层上的裂纹阻挡层。裂缝止动器为具有至少两个开口的中空圆筒形状。

10. 发明申请

US20130175705A1 Stress Compensation Layer for 3D Packaging 有权
标题翻译： 3D包装应力补偿层
公开(公告)号：US20130175705A1
公开(公告)日：2013-07-11
申请号：US13348449
申请日：2012-01-11
申请人： Chun-Hung Lin , Yu-Feng Chen , Han-Ping Pu , Hung-Jui Kuo
发明人： Chun-Hung Lin , Yu-Feng Chen , Han-Ping Pu , Hung-Jui Kuo
IPC分类号： H01L23/52 , H01L21/56
CPC分类号： H01L23/562 , H01L21/565 , H01L23/3121 , H01L23/3128 , H01L23/49822 , H01L25/105 , H01L2224/16225 , H01L2225/1023 , H01L2225/1058 , H01L2924/01322 , H01L2924/15311 , H01L2924/15321 , H01L2924/18161 , H01L2924/3511 , H01L2924/00
摘要： A stress compensation for use in packaging, and a method of forming, is provided. The stress compensation layer is placed on an opposing side of a substrate from an integrated circuit die. The stress compensation layer is designed to counteract at least some of the stress exerted structures on the die side of the substrate, such as stresses exerted by a molding compound that at least partially encapsulates the first integrated circuit die. A package may also be electrically coupled to the substrate.
摘要翻译：提供了用于包装的应力补偿，以及形成方法。应力补偿层从集成电路管芯放置在衬底的相对侧上。应力补偿层被设计成抵抗基板的模具侧上的应力施加结构中的至少一些，例如由至少部分地封装第一集成电路管芯的模制化合物施加的应力。封装还可以电耦合到衬底。

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