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1. 发明授权

US08400190B2 Apparatus and method to tolerate floating input pin for input buffer 有权
标题翻译：允许输入缓冲器的浮动输入引脚的装置和方法
公开(公告)号：US08400190B2
公开(公告)日：2013-03-19
申请号：US12565624
申请日：2009-09-23
申请人： Chun-Hsiung Hung , Kuen-Long Chang , Nai-Ping Kuo , Hsieh-Ming Chih
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Nai-Ping Kuo , Hsieh-Ming Chih
IPC分类号： H03K3/00
CPC分类号： H03K3/00 , H03K19/0002 , H03K19/09425
摘要： An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.
摘要翻译：集成电路装置包括适于从内部或外部驱动器接收信号的焊盘以及包括耦合到焊盘的输入端的输入缓冲电路。输入缓冲器电路包括具有控制端子的传输晶体管，连接到焊盘的第一导电端子和连接到第一电压的第二导电端子。输入缓冲电路还包括具有电耦合到传输晶体管的控制端的端子的锁存器。所述输入缓冲器电路还包括耦合到所述锁存器的电路，所述电路包括反馈晶体管，所述反馈晶体管具有电耦合到所述焊盘的控制端子，电耦合到第二电压的第一导电端子以及耦合到所述锁存器的第二导电端子。

2. 发明申请

US20110068837A1 APPARATUS AND METHOD TO TOLERATE FLOATING INPUT PIN FOR INPUT BUFFER 有权
标题翻译：用于输入输入缓冲器的浮动输入引脚的装置和方法
公开(公告)号：US20110068837A1
公开(公告)日：2011-03-24
申请号：US12565624
申请日：2009-09-23
申请人： CHUN-HSIUNG HUNG , Kuen-Long Chang , Nai-Ping Kuo , Hsieh-Ming Chih
发明人： CHUN-HSIUNG HUNG , Kuen-Long Chang , Nai-Ping Kuo , Hsieh-Ming Chih
IPC分类号： H03L7/00 , H03K3/02
CPC分类号： H03K3/00 , H03K19/0002 , H03K19/09425
摘要： An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.
摘要翻译：集成电路装置包括适于从内部或外部驱动器接收信号的焊盘以及包括耦合到焊盘的输入端的输入缓冲电路。输入缓冲器电路包括具有控制端子的传输晶体管，连接到焊盘的第一导电端子和连接到第一电压的第二导电端子。输入缓冲电路还包括具有电耦合到传输晶体管的控制端的端子的锁存器。所述输入缓冲器电路还包括耦合到所述锁存器的电路，所述电路包括反馈晶体管，所述反馈晶体管具有电耦合到所述焊盘的控制端子，电耦合到第二电压的第一导电端子以及耦合到所述锁存器的第二导电端子。

3. 发明授权

US08599640B2 Method and apparatus of addressing a memory integrated circuit 有权
标题翻译：寻址存储器集成电路的方法和装置
公开(公告)号：US08599640B2
公开(公告)日：2013-12-03
申请号：US13708150
申请日：2012-12-07
申请人： Chun-Hsiung Hung , Kuen-Long Chang , Hsieh Ming Chih
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Hsieh Ming Chih
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12
摘要： A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.
摘要翻译：存储器集成电路具有访问存储器集成电路的存储单元的控制电路。控制电路响应于包括第一命令和第二命令的命令。第一个命令指定高位地址位集合。第二个命令指定低位地址位集合。地址位的高位集合和地址位的低位集合构成存储器集成电路的完整访问地址。第一个命令和第二个命令在命令代码中有所不同。

4. 发明授权

US08345505B2 Method and apparatus of addressing a memory integrated circuit 有权
公开(公告)号：US08345505B2
公开(公告)日：2013-01-01
申请号：US12769456
申请日：2010-04-28
申请人： Chun-Hsiung Hung , Kuen-Long Chang , Hsieh-Ming Chih
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Hsieh-Ming Chih
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12
摘要： A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.

5. 发明申请

US20130094319A1 Method and Apparatus of Addressing A Memory Integrated Circuit 有权
标题翻译：寻址存储器集成电路的方法和装置
公开(公告)号：US20130094319A1
公开(公告)日：2013-04-18
申请号：US13708150
申请日：2012-12-07
申请人： Chun-Hsiung Hung , Kuen-Long Chang , Hsieh Ming Chih
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Hsieh Ming Chih
IPC分类号： G11C8/10
CPC分类号： G11C8/10 , G11C8/12
摘要： A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.
摘要翻译：存储器集成电路具有访问存储器集成电路的存储单元的控制电路。控制电路响应于包括第一命令和第二命令的命令。第一个命令指定高位地址位集合。第二个命令指定低位地址位集合。地址位的高位集合和地址位的低位集合构成存储器集成电路的完整访问地址。第一个命令和第二个命令在命令代码中有所不同。

6. 发明申请

US20110128809A1 Method and Apparatus of Addressing A Memory Integrated Circuit 有权
标题翻译：寻址存储器集成电路的方法和装置
公开(公告)号：US20110128809A1
公开(公告)日：2011-06-02
申请号：US12769456
申请日：2010-04-28
申请人： Chun-Hsiung Hung , Kuen-Long Chang , Hsieh-Ming Chih
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Hsieh-Ming Chih
IPC分类号： G11C8/00
CPC分类号： G11C8/10 , G11C8/12
摘要： A memory integrated circuit has control circuitry that accesses memory cells of the memory integrated circuit. The control circuitry is responsive to commands including a first command and a second command. The first command specifies a high order set of address bits. The second command specifies a low order set of address bits. The high order set of address bits and the low order set of address bits constitute a complete access address of the memory integrated circuit. The first command and the second command have different in command codes.
摘要翻译：存储器集成电路具有访问存储器集成电路的存储单元的控制电路。控制电路响应于包括第一命令和第二命令的命令。第一个命令指定高位地址位集合。第二个命令指定低位地址位集合。地址位的高位集合和地址位的低位集合构成存储器集成电路的完整访问地址。第一个命令和第二个命令在命令代码中有所不同。

7. 发明授权

US08982640B2 Method and apparatus for reducing erase disturb of memory by using recovery bias 有权
标题翻译：通过使用恢复偏压来减少存储器的擦除干扰的方法和装置
公开(公告)号：US08982640B2
公开(公告)日：2015-03-17
申请号：US13426985
申请日：2012-03-22
申请人： Chun Hsiung Hung , Bo-Chang Wu , Kuen-Long Chang , Ken-Hui Chen
发明人： Chun Hsiung Hung , Bo-Chang Wu , Kuen-Long Chang , Ken-Hui Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/3431 , G11C16/14 , G11C16/3418 , G11C16/344
摘要： A nonvolatile memory array is divided into multiple memory groups. The nonvolatile memory array receives an erase command to erase a first set of the memory groups, and not a second set of the memory groups. The control circuitry is responsive to the erase command to erase the first set of memory groups, by applying a recovery bias arrangement that adjusts threshold voltages of memory cells in at least one memory group of the second set of memory groups. By applying the recovery bias arrangement to memory cells in at least one memory group of the second set of memory groups, erase disturb is corrected during the recovery bias arrangement, at least in part.
摘要翻译：非易失性存储器阵列被分成多个存储器组。非易失性存储器阵列接收擦除命令以擦除第一组存储器组，而不是第二组存储器组。控制电路响应于擦除命令来擦除第一组存储器组，通过应用恢复偏压布置来调整第二组存储器组的至少一个存储器组中的存储器单元的阈值电压。通过将恢复偏压装置应用于第二组存储器组的至少一个存储器组中的存储器单元，至少部分地在恢复偏压装置期间校正擦除干扰。

8. 发明授权

US08797802B2 Method and apparatus for shortened erase operation 有权
标题翻译：用于缩短擦除操作的方法和装置
公开(公告)号：US08797802B2
公开(公告)日：2014-08-05
申请号：US13536555
申请日：2012-06-28
申请人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo , Chin-Hung Chang , Chang-Ting Chen
发明人： Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo , Chin-Hung Chang , Chang-Ting Chen
IPC分类号： G11C11/34
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/14 , G11C29/34 , G11C2029/2602
摘要： A nonvolatile memory array has a multiple erase procedures of different durations. A block of memory cells of the array can be erased by one of the different erase procedures.
摘要翻译：非易失性存储器阵列具有不同持续时间的多个擦除过程。可以通过不同的擦除过程之一来擦除阵列的存储器单元的块。

9. 发明授权

US08677100B2 Serial memory interface for extended address space 有权
标题翻译：用于扩展地址空间的串行存储器接口
公开(公告)号：US08677100B2
公开(公告)日：2014-03-18
申请号：US12813395
申请日：2010-06-10
申请人： Yulan Kuo , Kuen-Long Chang , Chun-Hsiung Hung
发明人： Yulan Kuo , Kuen-Long Chang , Chun-Hsiung Hung
IPC分类号： G06F9/34
CPC分类号： G06F9/30076 , G06F9/30189 , G06F9/342
摘要： An integrated circuit memory device has a memory array and control logic with at least a first addressing mode in which the instruction includes a first instruction code and an address of a first length; and a second addressing mode in which the instruction includes the first instruction code and an address of a second length. The first length of the address is different from the second length of the address.
摘要翻译：集成电路存储器件具有存储器阵列和具有至少第一寻址模式的控制逻辑，其中指令包括第一指令代码和第一长度的地址; 以及第二寻址模式，其中指令包括第一指令代码和第二长度的地址。地址的第一个长度与地址的第二个长度不同。

10. 发明申请

US20130326184A1 MEMORY APPARATUS 有权
标题翻译：记忆装置
公开(公告)号：US20130326184A1
公开(公告)日：2013-12-05
申请号：US13584393
申请日：2012-08-13
申请人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
发明人： Yu-Meng Chaung , Chun-Hsiung Hung , Kuen-Long Chang , Ken-Hui Chen , Nai-Ping Kuo
IPC分类号： G06F12/00
CPC分类号： G11C7/1072 , G11C7/1066 , G11C7/222 , G11C2207/104
摘要： A memory apparatus includes a host device and a slave device. The host device stores verification data. The slave device includes a memory unit, a control unit, and a logic unit. The control unit drives the memory unit to provide storage data in a data transmission sub-period, and further provides a control signal, indicating the first verification data, in a dummy sub-period. The logic unit provides first preamble data, indicating substantially a same data value as the verification data, in the dummy sub-period in response to the first control signal. The preamble data and the storage data are transmitted according to an internal clock signal. The host device samples the first preamble data according to an external clock signal, and determines whether the external and the internal clock signals are synchronized by comparing the first preamble data and the first verification data.
摘要翻译：存储装置包括主机装置和从装置。主机设备存储验证数据。从设备包括存储器单元，控制单元和逻辑单元。控制单元驱动存储单元以在数据传输子时段中提供存储数据，并且还在虚拟子周期中提供指示第一验证数据的控制信号。逻辑单元响应于第一控制信号，在虚拟子周期中提供与验证数据基本上相同的数据值的第一前同步码数据。前导码数据和存储数据根据内部时钟信号发送。主机设备根据外部时钟信号对第一前同步码数据进行采样，并且通过比较第一前导码数据和第一验证数据来确定外部和内部时钟信号是否被同步。

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